Three-dimensionally stacked nonvolatile semiconductor memory

Abstract

A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.

What is claimed is: 
     
       1. A three-dimensionally stacked nonvolatile semiconductor memory comprising:
 a memory cell array provided in a semiconductor substrate;   conductive layers stacked above the semiconductor substrate in the memory cell array in such a manner as to be insulated from one another;   a bit line which is disposed above the conductive layers in such a manner as to be insulated from the conductive layers;   a semiconductor column which extends through the conductive layers and which has an upper end connected to the bit line and a lower end connected to the semiconductor substrate;   word lines for which the conductive layers except for the uppermost and lowermost conductive layers are used;   memory cells provided at intersections of word lines and the semiconductor column, respectively;   a register circuit which retains operation setting information for the memory cell array and which has information to supply a potential suitable for each of the word lines; and   a potential control circuit which controls the potentials supplied to the word lines and which reads the information retained in the register circuit in accordance with a position of a word line in a direction perpendicular to the surface of the semiconductor substrate and which supplies a potential suitable for the word line corresponding to an input address signal.   
     
     
       2. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 1 , wherein
 the register circuit has registers which retain potential codes indicating the potentials suitable for the word lines, respectively, and   the potential control circuit selects the potential code corresponding to the input address signal from registers, and supplies the suitable potential to the word line corresponding to the input address signal in accordance with the selected potential code.   
     
     
       3. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 1 , wherein
 the register circuit has   a first register which retains, as a reference code, a value indicating the potential suitable for one of the word lines, and   one or more second registers which are respectively provided to correspond to the remaining word lines except for the one word line corresponding to the reference code and which retain a difference code between the reference code and a value indicating the potential suitable for each of the remaining word lines; and   the potential control circuit selects the difference code corresponding to the input address signal from the one or more second registers, and supplies the suitable potential to a word line corresponding to the input address signal in accordance with a calculation result obtained from the selected difference code and the reference code.   
     
     
       4. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 1 , wherein
 the register circuit has first and second registers which retain first and second coefficients of an approximation function, respectively, and   the potential control circuit uses the input address signal as a variable of the approximation function, and supplies the suitable potential to the word line corresponding to the input address signal in accordance with the approximation function using the first and second coefficients.   
     
     
       5. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 1 , further comprising:
 an external device which externally controls the operation of the memory cell array,   wherein the potential suitable for each of the word lines is set by an instruction from the external device.   
     
     
       6. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 1 , wherein
 the potential control circuit has   an arithmetic unit which outputs a value indicating the potential supplied to the one word line in accordance with an output of the register circuit and the address signal,   a converter which outputs a converted value of the value indicating the potential supplied to the one word line,   a comparator which outputs a comparison value between a reference value and the converted value, and   a potential generator which generates a potential suitable for each of the word lines in accordance with the comparison value.   
     
     
       7. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 1 , wherein
 the uppermost conductive layer is a straight first select gate line extending in a second direction intersecting with a first direction, and   the lowermost conductive layer is a plate-like second select gate line.   
     
     
       8. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 1 , wherein
 the potential supplied to upper one of word lines is equal to or more than the potential supplied to lower one of the word lines.   
     
     
       9. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 1 , wherein
 the memory cell has an insulating film functioning as a charge storage layer.   
     
     
       10. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 3 , wherein
 the number of bits indicating the difference value in each of the second registor is smaller than the number of bits indicating the reference value in the first registor.   
     
     
       11. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 3 , wherein the difference code using writing operation differs from the difference code using reading operation. 
     
     
       12. The three-dimensionally stacked nonvolatile semiconductor memory according to  claim 1 , wherein
 at least one of the operation setting information and the information to supply a potential suitable for each of the word lines includes adjusted values in each of the word lines to supply the potential suitable for the word line, and the adjusted values are determined based on arithmetic processing for driving results of each of the word lines.   
     
     
       13. A reading method for a semiconductor memory, the semiconductor memory including a first conductive layer, a second conductive layer, a third conductive layer, and a semiconductor column which extends in a first direction perpendicular to the first conductive layer and penetrates through the first conductive layer, the second conductive layer and the third conductive layer, the reading method comprising:
 applying a first read voltage for reading first level data to the first conductive layer when a first storage portion which is disposed between the first conductive layer and the semiconductor column is selected;   applying a second read voltage for reading the first level data to the second conductive layer when a second storage portion which is disposed between the second conductive layer and the semiconductor column is selected; and   applying a third read voltage for reading the first level data to the third conductive layer when a third storage portion which is disposed between the third conductive layer and the semiconductor column is selected,   wherein the third read voltage is larger than the second read voltage, and the second read voltage is larger than the first read voltage, and   wherein a third diameter of the semiconductor column surrounded by the third storage portion in a second direction perpendicular to the first direction is larger than a second diameter of the semiconductor column surrounded by the second storage portion in the second direction, and the second diameter of the semiconductor column is larger than a first diameter of the semiconductor column surrounded by the first storage portion in the second direction.   
     
     
       14. The reading method according to claim 13, wherein
 a first un-selection voltage is applied to the first conductive layer when the second conductive layer is selected,   a second un-selection voltage is applied to the second conductive layer when the first conductive layer is selected, the first un-selection voltage being different from the second un-selection voltage, and   a third un-selection voltage different from the first and second un-selection voltages is applied to the third conductive layer when either of the first and second conductive layers is selected.   
     
     
       15. The reading method according to claim 14, wherein
 the first un-selection voltage is lower than the second and third un-selection voltages.   
     
     
       16. The reading method according to claim 13, wherein
 the third conductive layer is disposed above the first and second conductive layers, and   the second conductive layer is disposed between the first and third conductive layers.   
     
     
       17. The reading method according to claim 13, wherein
 the first storage portion is configured as a first memory cell, a gate of the first memory cell being electrically connected to the first conductive layer configured as a first word line,   the second storage portion is configured as a second memory cell, a gate of the second memory cell being electrically connected to the second conductive layer configured as a second word line, and   the third storage portion is configured as a third memory cell, a gate of the third memory cell being electrically connected to the third conductive layer configured as a third word line.   
     
     
       18. The reading method according to claim 17, wherein
 the first word line, the first storage portion, and a portion of the semiconductor column surrounded by the first storage portion are disposed along the second direction,   the second word line, the second storage portion, and a portion of the semiconductor column surrounded by the second storage portion are disposed along the second direction, and   the third word line, the third storage portion, and a portion of the semiconductor column surrounded by the third storage portion are disposed along the second direction.   
     
     
       19. A programing method for a semiconductor memory, the semiconductor memory including a first conductive layer, a second conductive layer, a third conductive layer, and a semiconductor column which extends in a first direction perpendicular to the first conductive layer and penetrates through the first conductive layer, the second conductive layer and the third conductive layer, the programing method comprising:
 applying a first program voltage to the first conductive layer when a first storage portion which is disposed between the first conductive layer and the semiconductor column is selected;   applying a second program voltage to the second conductive layer when a second storage portion which is disposed between the second conductive layer and the semiconductor column is selected; and   applying a third program voltage to the third conductive layer when a third storage portion which is disposed between the third conductive layer and the semiconductor column is selected,   wherein the third program voltage is larger than the second program voltage, and the second program voltage is larger than the first program voltage, and   wherein a third diameter of the semiconductor column surrounded by the third storage portion in a second direction perpendicular to the first direction is larger than a second diameter of the semiconductor column surrounded by the second storage portion in the second direction, and the second diameter of the semiconductor column is larger than a first diameter of the semiconductor column surrounded by the first storage portion in the second direction.   
     
     
       20. The programming method according to claim 19, wherein
 a first un-selection voltage is applied to the first conductive layer when the second conductive layer is selected,   a second un-selection voltage is applied to the second conductive layer when the first conductive layer is selected, the first un-selection voltage being different from the second un-selection voltage, and   a third un-selection voltage different from the first and second un-selection voltages is applied to the third conductive layer when either of the first and second conductive layers is selected.   
     
     
       21. The programing method according to claim 20, wherein
 the first un-selection voltage is lower than the second and third un-selection voltages.   
     
     
       22. The programing method according to claim 19, wherein
 the third conductive layer is disposed above the first and second conductive layers, and   the second conductive layer is disposed between the first and third conductive layers.   
     
     
       23. The programing method according to claim 19, wherein
 the first storage portion is configured as a first memory cell, a gate of the first memory cell being electrically connected to the first conductive layer configured as a first word line,   the second storage portion is configured as a second memory cell, a gate of the second memory cell being electrically connected to the second conductive layer configured as a second word line, and   the third storage portion is configured as a third memory cell, a gate of the third memory cell being electrically connected to the third conductive layer configured as a third word line.   
     
     
       24. The programing method according to claim 23, wherein
 the first word line, the first storage portion, and a portion of the semiconductor column surrounded by the first storage portion are disposed along the second direction,   the second word line, the second storage portion, and a portion of the semiconductor column surrounded by the second storage portion are disposed along the second direction, and   the third word line, the third storage portion, and a portion of the semiconductor column surrounded by the third storage portion are disposed along the second direction.