Method and system for a serial peripheral interface

Abstract

An integrated circuit includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently.

What is claimed is: 
     
       1. An integrated circuit, comprising:
 a memory array having a plurality of memory addresses at which to store data;   a serial peripheral interface coupled to the memory array, the serial peripheral interface including a plurality of pins; and   circuitry performing a first transfer of the data through the plurality of pins of the serial peripheral interface, while performing a second transfer of one of the plurality of memory addresses through the plurality of pins of the serial peripheral interface, wherein at least one of the first transfer and the second transfer is performed concurrently through multiple pins of the plurality of pins of the serial peripheral interface.   
     
     
       2. The integrated circuit of  claim 1 , wherein the operation circuitry performs the first transfer as part of a first read operation, and performs the second transfer as part of a second read operation. 
     
     
       3. The integrated circuit of  claim 1 , wherein the first transfer is performed while the second transfer is performed, in that at least one bit of the first transfer is performed through the plurality of pins at a same time as at least one bit of the second transfer is performed through the plurality of pins. 
     
     
       4. The integrated circuit of  claim 1 , wherein the operation circuitry uses a falling edge or a rising edge or both the falling and the rising edges of a clock signal to trigger a bit transfer through the plurality of pins. 
     
     
       5. An integrated circuit, comprising:
 a memory array;   a serial peripheral interface coupled to the memory array, the serial peripheral interface including a plurality of pins; and   circuitry performing a first transfer of read operation bits through the plurality of pins of the serial peripheral interface, simultaneously with a second transfer of write operation bits through the plurality of pins of the serial peripheral interface, wherein at least one of the first transfer and the second transfer is performed concurrently through multiple pins of the plurality of pins of the serial peripheral interface.   
     
     
       6. The integrated circuit of  claim 1 , wherein the write operation bits include a program instruction, a program address of the memory array, and data bits to be written to the memory array at the program address. 
     
     
       7. The integrated circuit of  claim 1 , wherein the read operation bits include data bits read from the memory array. 
     
     
       8. The integrated circuit of  claim 1 , wherein the first transfer is performed simultaneously with the second transfer, in that at least one bit of the first transfer is performed through the plurality of pins at a same time as at least one bit of the second transfer is performed through the plurality of pins. 
     
     
       9. The integrated circuit of  claim 1 , wherein the operation circuitry uses a falling edge or a rising edge or both the falling and the rising edges of a clock signal to trigger a bit transfer through the plurality of pins. 
     
     
       10. An integrated circuit, comprising:
 a memory array;   a serial peripheral interface coupled to the memory array, the serial peripheral interface including a plurality of pins; and   circuitry performing a first transfer of read operation bits through the plurality of pins of the serial peripheral interface, simultaneously with a second transfer of erase operation bits through the plurality of pins of the serial peripheral interface, wherein at least one of the first transfer and the second transfer is performed concurrently through multiple pins of the plurality of pins of the serial peripheral interface.   
     
     
       11. The integrated circuit of  claim 1 , wherein the erase operation bits include an erase instruction, and an erase address of the memory array. 
     
     
       12. The integrated circuit of  claim 1 , wherein the read operation bits include data bits read from the memory array. 
     
     
       13. The integrated circuit of  claim 1 , wherein the first transfer is performed simultaneously with the second transfer, in that at least one bit of the first transfer is performed through the plurality of pins at a same time as at least one bit of the second transfer is performed through the plurality of pins. 
     
     
       14. The integrated circuit of  claim 1 , wherein the operation circuitry uses a falling edge or a rising edge or both the falling and the rising edges of a clock signal to trigger a bit transfer through the plurality of pins. 
     
     
       15. An integrated circuit, comprising:
 a memory array;   a serial peripheral interface coupled to the memory array, the serial peripheral interface including a plurality of pins; and   circuitry performing a first transfer of read operation bits of a first read operation through the plurality of pins of the serial peripheral interface, simultaneously with a second transfer of read operation bits of a second read operation through the plurality of pins of the serial peripheral interface, wherein at least one of the first transfer and the second transfer is performed concurrently through multiple pins of the plurality of pins of the serial peripheral interface.   
     
     
       16. The integrated circuit of  claim 1 , wherein the read operation bits of the first read operation include a read instruction, and a read address of the memory array. 
     
     
       17. The integrated circuit of  claim 1 , wherein the read operation bits of the second read operation include data bits read from the memory array. 
     
     
       18. The integrated circuit of  claim 1 , wherein the first transfer is performed simultaneously with the second transfer, in that at least one bit of the first transfer is performed through the plurality of pins at a same time as at least one bit of the second transfer is performed through the plurality of pins. 
     
     
       19. The integrated circuit of  claim 1 , wherein the operation circuitry uses a falling edge or a rising edge or both the falling and the rising edges of a clock signal to trigger a bit transfer through the plurality of pins. 
     
     
       20. An integrated circuit, comprising:
 a memory array having a plurality of addressable locations with associated memory addresses at which to store data;   a serial peripheral interface, the serial peripheral interface including a plurality of pins; and   circuitry performing a first transfer of data bits through the serial peripheral interface on a first pin in the plurality of pins, the data bits of the first transfer responsive to address bits for access to addressable locations in the memory array received on a second pin in the plurality of pins, while performing a second transfer of memory address bits of a memory address of an addressable location in the plurality of addressable locations in the memory array on said second pin of the plurality of pins concurrently with the data bits of the first transfer on the first pin through the serial peripheral interface.    
     
     
       21. The integrated circuit of claim 20, wherein the circuitry performs the first transfer and the second transfer as part of a read/write operation.  
     
     
       22. The integrated circuit of claim 20, wherein the circuitry triggers bit transfers through the plurality of pins on both falling and rising edges of a clock signal.  
     
     
       23. An integrated circuit, comprising:
 an addressable memory;   a serial peripheral interface coupled to the memory, the serial peripheral interface including a plurality of pins; and   circuitry performing a first transfer of data bits on a first pin of the serial peripheral interface of a read operation addressed to the addressable memory responsive to a command received on a second pin of the serial peripheral interface, simultaneously with a second transfer of address bits of a write operation addressed to the addressable memory on the second pin of the serial peripheral interface.    
     
     
       24. The integrated circuit of claim 23, wherein the write operation includes transfer of program instruction bits, program address bits of a program address in the memory array, and data bits to be written to the memory array at the program address.  
     
     
       25. The integrated circuit of claim 23, wherein the read operation includes transfer of data bits read from the memory.  
     
     
       26. The integrated circuit of claim 23, wherein the first transfer is performed simultaneously with the second transfer, in that at least one bit of the first transfer is performed at a same time as at least one bit of the second transfer is performed.  
     
     
       27. The integrated circuit of claim 23, wherein the operation circuitry triggers bit transfers through the plurality of pins on both falling and rising edges of a clock signal.  
     
     
       28. A method for operating an integrated circuit having a serial peripheral interface, comprising:
 performing a first transfer of data bits on a first pin of the serial peripheral interface of a read operation for data stored in an addressable memory responsive to a command received on a second pin of the serial peripheral interface, while performing a second transfer of address bits of a memory address of a location in the addressable memory through the second pin of the serial peripheral interface; and   triggering a bit transfer on a falling edge and a bit transfer on a rising edge of a clock signal in one or both of the first and second transfers.    
     
     
       29. The method of claim 28, wherein the first transfer and second transfer are part of a read/write operation.  
     
     
       30. The method of claim 28, wherein the first transfer is performed while the second transfer is performed, in that at least one data bit of the first transfer is performed at a same time as at least one address bit of the second transfer is performed.