Nonvolatile memory device, read method for nonvolatile memory device, and memory system incorporating nonvolatile memory device

Abstract

A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times.

What is claimed is: 
     
       1. A method of reading a nonvolatile memory device including a plurality of nonvolatile memory cells, the method comprising:
 receiving a read command and a read address;   in response to the read command, reading data from first memory cells corresponding to the read address among the plurality of nonvolatile memory cells;   receiving a read enable signal, the read enable signal being toggled after the receiving the read command and the read address;   generating a strobe signal based on the read enable signal;   outputting the strobe signal to an external device; and   outputting, to the external device, the data read from the first memory cells in synchronization with the strobe signal in response to a latency value, the latency value being corresponding to the number of toggling of the strobe signal between the receiving the read command and the read address and the outputting the data, the latency value being zero or a positive integer,   wherein the read enable signal remains constant while the read command and the read address are received, and   the latency value is stored in the nonvolatile memory device and is programmable with a set command.   
     
     
       2. The method of  claim 1 , wherein the outputting the data includes:
 generating a delayed clock by delaying the read enable signal based on the latency value; and   outputting the data in response to the delayed clock.   
     
     
       3. The method of  claim 2 , wherein the data is output in synchronization with a first rising edge and a first falling edge of the strobe signal after the receiving the read command and the read address when the latency value is zero. 
     
     
       4. The method of  claim 2 , wherein the outputting the data starts from a second rising edge or a second falling edge of the strobe signal after the receiving the read command and the read address when the latency value is one. 
     
     
       5. The method of  claim 1 , wherein the nonvolatile memory device includes a three dimensional memory array including a plurality of memory cell strings. 
     
     
       6. A nonvolatile memory device, comprising:
 a plurality of nonvolatile memory cells included in the nonvolatile memory device;   a program circuit configured to store a latency value;   an address decoder configured to receive a read address and configured to select at least one memory cell corresponding to the read address among the plurality of nonvolatile memory cells;   a control logic configured to receive a read command and a read enable signal;   a read and write circuit configured to read data from the at least one of the memory cell in response to the read command; and   an input/output driver configured to generate a strobe signal in response to the read enable signal, configured to output the strobe signal to an external device, and configured to output to the external device the data in synchronization with the strobe signal,   wherein outputting the data read from the at least one of the memory cell starts after the strobe signal is toggled N times, N is corresponding to a latency value   the read enable signal is not toggled during the read command is received by the control circuit and the read address is received by the address decoder,   the read enable signal is toggled after the read command is received by the control circuit and the read address is received by the address decoder, and   the latency value is programmable using a set command provided by the external device.   
     
     
       7. The nonvolatile memory device of  claim 6 , further comprising a clock generator configured to generate a clock delaying the read enable signal. 
     
     
       8. The nonvolatile memory device of  claim 7 , wherein the read and write circuit configured to provide the data to the input/output driver in response to the clock. 
     
     
       9. The nonvolatile memory device of  claim 8 , wherein the clock generator is configured to generator the clock in response to the latency value. 
     
     
       10. The nonvolatile memory device of  claim 7 , wherein the memory cell array includes a three dimensional memory array, the three dimensional memory array including a plurality of memory cell strings. 
     
     
       11. A nonvolatile memory system, comprising:
 a controller configured to provide a read enable signal, a read command and a read address; and   a nonvolatile memory device including a plurality of nonvolatile memory cells, configured to read data from first memory cells corresponding to the read address among the plurality of nonvolatile memory cells in response to the read command, configured to generate a strobe signal in response to the read enable signal, and configured to store a latency value;   wherein the nonvolatile memory device is configured to output the data to the controller in synchronization with the strobe signal in response to the latency value;   the controller configured to control the read enable signal remaining constant while the read command and the read address are received by the nonvolatile memory device, and configured to control the read enable signal toggling after the read command and the read address are received by the nonvolatile memory device,   a start of the outputting the data occurs after the strobe signal is toggled N times, N being a value corresponding to the latency value, and   the latency value is programmable with a set command.   
     
     
       12. The nonvolatile memory system of  claim 11 , wherein, when the latency value is zero, the data is output in synchronization with a first rising edge and a first falling edge of the strobe signal after the read address is received. 
     
     
       13. The nonvolatile memory system of  claim 11 , wherein, when the latency value is one, the start of the outputting the data occurs from a second rising edge or a second falling edge of the strobe signal after the receiving the read command and the read address. 
     
     
       14. The nonvolatile memory system of  claim 11 , wherein the nonvolatile memory device is configured generate a delayed clock by delaying the read enable signal based on the latency value and to output the data in response to the delayed clock. 
     
     
       15. The nonvolatile memory system of  claim 11 , wherein the nonvolatile memory device includes a three dimensional nonvolatile memory array, the three dimensional nonvolatile memory array including a plurality of memory cell strings. 
     
     
       16. A method of reading a nonvolatile memory device, comprising:
 receiving a read command and a read address;   reading data from a plurality of nonvolatile memory cells corresponding to the read address in response to the read command, the plurality of nonvolatile memory cells being included in the nonvolatile memory device,   receiving a read enable signal;   generating a strobe signal in response to toggling of the read enable signal; and   outputting the data read from the plurality of nonvolatile memory cells together with the strobe signal to an external device, wherein a start of the outputting the data occurs after the strobe signal is toggled N times, N being a value corresponding to a latency value, the latency value being programmable by a set command,   wherein the read enable signal remains constant while the read command and the read address are received, and   the read enable signal is toggled after the read command and the read address are received.   
     
     
       17. The method of  claim 16 , wherein the data is output in synchronization with rising edges and falling edges of the strobe signal. 
     
     
       18. The method of  claim 16 , wherein the data is output in synchronization with a first rising edge and a first falling edge of the strobe signal when the latency option is zero. 
     
     
       19. The method of  claim 16 , wherein the outputting the data includes:
 generating a delayed clock by delaying the read enable signal based on the latency value; and   outputting the data in response to the delayed clock.   
     
     
       20. The method of  claim 16 , wherein the nonvolatile memory device includes a three dimensional nonvolatile memory array, the three dimensional nonvolatile memory array including a plurality of memory cell strings. 
     
     
       21. A memory controller, comprising:
 an input/output driver configured to:   transmit a register setting value of a nonvolatile memory device;   transmit a read command and a read address;   transmit a read enable signal;   receive a read data corresponding to the read address;   receive a strobe signal, the strobe signal toggling during receiving the read data and further toggling a predetermined number of times immediately before receiving the read data; and   receive a dummy data in synchronization with the strobe signal further toggling the predetermined number of times,   wherein the strobe signal is generated based on the read enable signal after a first delay time from the read enable signal starting toggling regardless of the predetermined number of times.    
     
     
       22. The memory controller of claim 21, wherein the predetermined number of times is set based on the register setting value.  
     
     
       23. The memory controller of claim 22, wherein the predetermined number of times is set into one of zero clock cycle, one clock cycle and two clock cycle.  
     
     
       24. The memory controller of claim 23, wherein both the read data and the dummy data are received through identical input/output signal (DQ) terminals.  
     
     
       25. The memory controller of claim 24, wherein the dummy data is based on the read address.  
     
     
       26. A method of operating a controller for controlling a nonvolatile memory device, the method comprising:
 transmitting a register setting value of the nonvolatile memory device;   transmitting a read command and a read address to the nonvolatile memory device;   transmitting a read enable signal to the nonvolatile memory device;   receiving a strobe signal from the nonvolatile memory device, the strobe signal being generated based on the read enable signal and toggling during data output period of the nonvolatile memory device; and   receiving a read data corresponding to the read address from the nonvolatile memory device in synchronization with the strobe signal,   wherein the strobe signal further toggles a predetermined number of times immediately before receiving the read data, and a dummy data is received in synchronization with the strobe signal toggling the predetermined number of times.    
     
     
       27. The method of claim 26, wherein the predetermined number of times is set based on the register setting value.  
     
     
       28. The method of claim 27, wherein the predetermined number of times is set into one of zero clock cycle, one clock cycle and two clock cycle.  
     
     
       29. The method of claim 28, wherein both the read data and the dummy data are received through identical input/output signal (DQ) terminals.  
     
     
       30. The method of claim 29, wherein the strobe signal is generated after a first delay time from starting toggling of the read enable signal regardless of the predetermined number of times.  
     
     
       31. The method of claim 30, wherein the dummy data is based on the read address.  
     
     
       32. A method of operating a controller for controlling a nonvolatile memory device, the method comprising:
 transmitting a register setting value of the nonvolatile memory device;   transmitting a read command and a read address to the nonvolatile memory device;   transmitting a read enable signal to the nonvolatile memory device;   receiving a strobe signal from the nonvolatile memory device, the strobe signal being generated based on the read enable signal and toggling during data output period of the nonvolatile memory device; and   receiving a read data corresponding to the read address from the nonvolatile memory device in synchronization with the strobe signal,   wherein the strobe signal further toggles a predetermined number of times immediately before receiving the read data and the strobe signal is generated after a first delay time from the read enable signal starting toggling regardless of the predetermined number of times.    
     
     
       33. The method of claim 32, wherein the predetermined number of times is set based on the register setting value.  
     
     
       34. The method of claim 33, wherein the predetermined number of times is set into one of zero clock cycle, one clock cycle and two clock cycle.  
     
     
       35. The method of claim 32, further receiving a dummy data in synchronization with the strobe signal toggling the predetermined number of times.  
     
     
       36. The method of claim 35, wherein both the read data and the dummy data are received through identical input/output signal (DQ) terminals.  
     
     
       37. The method of claim 36, wherein the dummy data is based on the read address.  
     
     
       38. A memory system comprising:
 a controller configured to:   transmit a register setting value;   transmit a read command and a read address;   transmit a read enable signal; and   a nonvolatile memory device configured to:   transmit the strobe signal generated based on the read enable signal, the strobe signal toggles during data output period of the nonvolatile memory device; and   transmit a read data corresponding to the read address in synchronization with a strobe signal, the read data are transmitted after the strobe signal further toggling predetermined number of times,   wherein the strobe signal is generated after a first delay time from the toggling of the read enable signal regardless of the predetermined number of times.    
     
     
       39. The memory system of claim 38, wherein the predetermined number of times is set based on the register setting value.  
     
     
       40. The memory system of claim 39, wherein the predetermined number of times is set into one of zero clock cycle, one clock cycle and two clock cycle.  
     
     
       41. The memory system of claim 38, wherein further configured to receive a dummy data in synchronization with the strobe signal toggling the predetermined number of times.  
     
     
       42. The memory system of claim 41, wherein both the read data and the dummy data are received through identical input/output signal (DQ) terminals.  
     
     
       43. The memory system of claim 42, wherein the dummy data is based on the read address.  
     
     
       44. A memory controller, comprising:
 an input/output driver configured to:   transmit a register setting value of a nonvolatile memory device;   transmit a read command and a read address;   transmit a read enable signal;   receive a read data corresponding to the read address;   receive a strobe signal, the strobe signal toggling during receiving the read data and further toggling a predetermined number of times immediately before receiving the read data,   wherein the strobe signal is generated based on the read enable signal after a first delay time from the read enable signal starting toggling regardless of the predetermined number of times.    
     
     
       45. The memory controller of claim 44, wherein the predetermined number of times is set based on the register setting value.  
     
     
       46. The memory controller of claim 45, wherein the predetermined number of times is set into one of zero clock cycle, one clock cycle and two clock cycle.  
     
     
       47. The memory controller of claim 44, wherein a dummy data is received in synchronization with the strobe signal toggling the predetermined number of times.  
     
     
       48. The memory controller of claim 47, wherein both the read data and the dummy data are received through identical input/output signal (DQ) terminals.  
     
     
       49. The memory controller of claim 48, wherein the dummy data is based on the read address.  
     
     
       50. A memory controller, comprising:
 an input/output driver configured to:   transmit a register setting value of a nonvolatile memory device;   transmit a read command and a read address;   transmit a read enable signal;   receive a read data corresponding to the read address;   receive a strobe signal, the strobe signal toggling during receiving the read data and further toggling a predetermined number of times immediately before receiving the read data; and   receive a dummy data in synchronization with the strobe signal further toggling the predetermined number of times,   wherein the strobe signal is generated based on the read enable signal.    
     
     
       51. The memory controller of claim 50, wherein the predetermined number of times is set based on the register setting value.  
     
     
       52. The memory controller of claim 51, wherein the predetermined number of times is set into one of zero clock cycle, one clock cycle and two clock cycle.  
     
     
       53. The memory controller of claim 50, wherein both the read data and the dummy data are received through identical input/output signal (DQ) terminals.  
     
     
       54. The memory controller of claim 53, wherein the strobe signal is generated after a first delay time from the toggling of the read enable signal regardless of the predetermined number of times.  
     
     
       55. The memory controller of claim 54, wherein the dummy data is based on the read address.