Memory system and electronic device

Abstract

An electronic device includes a memory controller; a first memory device coupled to the memory controller; a second memory device coupled to the memory controller, the second memory device being a different type of memory from the first memory device; and a conversion circuit between the memory controller and the second memory device. The memory controller is configured to send a first command and first data to the first memory device according to a first timing scheme to access the first memory device, and send a second command and a packet to the conversion circuit according to the first timing scheme to access the second memory device. The conversion circuit is configured to receive the second command and the packet, and access the second memory device based on the second command and the packet.

What is claimed is: 
     
       1. An electronic device comprising:
 a memory controller;   a first memory device coupled to the memory controller;   a second memory device coupled to the memory controller, the second memory device being a different type of memory from the first memory device; and   a conversion circuit between the memory controller and the second memory device,   wherein the memory controller is configured to:
 send a first command and first data to the first memory device according to a first timing scheme to access the first memory device, and 
 send a second command and a packet to the conversion circuit according to the first timing scheme to access the second memory device, and 
   wherein the conversion circuit is configured to:
 receive the second command and the packet, and access the second memory device based on the second command and the packet, and 
   wherein:   the packet includes a header code, a tail code, and additional information, and   the conversion circuit is configured to strip the header code and the tail code, and to access the second memory device using the additional information.   
     
     
       2. The electronic device of  claim 1 , wherein the conversion circuit is configured to access the second memory device based on the second command and the packet according to a second timing scheme different from the first timing scheme. 
     
     
       3. The electronic device of  claim 2 , wherein the first memory device is configured to communicate directly with the memory controller using a first communication protocol that employs the first timing scheme, and the second memory device is configured to communicate with the memory controller through the conversion circuit using a second communication protocol that employs the second timing scheme. 
     
     
       4. The electronic device of  claim 2 , wherein:
 the first timing scheme is a timing scheme used for accessing a volatile memory; and   the second timing scheme is a timing scheme used for accessing a non-volatile memory.   
     
     
       5. The electronic device of  claim 1 , wherein the memory controller is further configured to:
 transmit a chip select signal that selects one of the first memory device and the second memory device.   
     
     
       6. The electronic device of  claim 1 , wherein at least one of the first memory device and the second memory device includes a three-dimensional memory array in which word-lines and/or bit-lines are shared between levels. 
     
     
       7. An electronic device configured to communicate with a memory controller, the electronic device comprising:
 a first memory device configured to be coupled directly to the memory controller;   a conversion circuit; and   a second memory device configured to be coupled indirectly to the memory controller through the conversion circuit, the second memory device being a different type of memory from the first memory device,   wherein the first memory device is configured to communicate directly with the memory controller in response to a first type of access command transmitted from the memory controller,   wherein the second memory device is configured to communicate indirectly with the memory controller through the conversion circuit, and   wherein the conversion circuit is configured to:
 communicate with the memory controller in response to the first type of access command transmitted from the memory controller, 
 receive a packet from the memory controller, wherein the packet includes a header code, a tail code, and additional information, and 
 strip the header code and the tail code, and to access the second memory device using the additional information. 
   
     
     
       8. The electronic device of  claim 7 , wherein:
 the conversion circuit is configured to communicate with the second memory device using a second type of access command different from the first type of access command.   
     
     
       9. The electronic device of  claim 8 , wherein:
 the first type of access command is a volatile memory access command, and   the second type of access command is a non-volatile memory access command.   
     
     
       10. The electronic device of  claim 8 , wherein:
 the conversion circuit is further configured to receive the first type of access command from the memory controller, and based on the access command and other information received from the memory controller in association with the command, transmit the second type of access command to the second memory device.   
     
     
       11. A memory system comprising:
 a first memory device that uses a first communication protocol for read and write operations;   a second memory device that uses a second communication protocol different from the first communication protocol for read and write operations;   a conversion circuit in communication with the second memory device; and   a memory controller configured to generate a first command and a first address in a first operation mode and to access the first memory device using the first command, the first address, and the first communication protocol in the first operation mode, and configured to generate a second command in a second operation mode, to access the second memory device through the conversion circuit, and to communicate with the conversion circuit using the second command and the first communication protocol,   wherein the first command and the second command are both commands used for the first communication protocol,   wherein the conversion circuit receives the second command and communicates with the second memory device using the second communication protocol, and   wherein the conversion circuit is configured to:
 receive a packet from the memory controller, wherein the packet includes a header code, a tail code, and additional information, and 
 strip the header code and the tail code, and to access the second memory device using the additional information. 
   
     
     
       12. The memory system of  claim 11 , wherein the memory controller is configured to:
 transmit the first command and the first address to the first memory device through a first channel based on an operation timing of the first communication protocol in the first operation mode, and   transmit the second command to the conversion circuit through the first channel based on the operation timing of the first communication protocol in the second operation mode.   
     
     
       13. The memory system of  claim 12 , wherein:
 when the first command is a first write command and the first address is a first write address:   the memory controller is configured to access the first memory device by transmitting write data to the first memory device through the first channel in the first operation mode, and   the write data is transmitted to the first memory device within a first period after the first write command and the first write address are transmitted to the first memory device through the first channel.   
     
     
       14. The memory system of  claim 13 , wherein
 when the first command is a first read command and the first address is a first read address:   the memory controller is configured to receive read data from the first memory device through the first channel in the first operation mode, and   the read data is received from the first memory device within the first period after the first read command and the first read address are transmitted to the first memory device through the first channel.   
     
     
       15. The memory system of  claim 13 , wherein
 when the second command is a second write command, the memory controller is configured to transmit a transmission packet to the conversion circuit through the first channel in the second operation mode, and   the transmission packet is transmitted to the conversion circuit within the first period after the second write command is transmitted to the conversion circuit through the first channel.   
     
     
       16. The memory system of  claim 15 , wherein
 when the second command is a second read command, the memory controller is configured to receive a reception packet from the conversion circuit through the first channel in the second operation mode, and   the reception packet is received from the conversion circuit within the first period after the second read command is transmitted to the conversion circuit through the first channel.   
     
     
       17. The memory system of  claim 16 , wherein
 the conversion circuit is configured to generate a read wait signal indicating that the conversion circuit is ready for transmitting the reception packet to the memory controller, and   the memory controller is configured to generate the second read command based on the read wait signal.   
     
     
       18. The memory system of  claim 15 , wherein
 when the transmission packet is a write transmission packet to store write data in the second memory device, the write transmission packet includes a transmission header code, an identification (ID) code, a write command code, a write address code, the write data and a transmission tail code.   
     
     
       19. The memory system of  claim 15 , wherein
 when the transmission packet is a read transmission packet to retrieve read data from the second memory device, the read transmission packet includes a transmission header code, an ID code, a read command code, a read address code and a transmission tail code.    
     
     
       20. A memory system comprising:
 a memory controller;   a first memory device coupled to the memory controller;   a conversion circuit coupled to the memory controller; and   a second memory device coupled to the conversion circuit, the second memory device being a different type of memory device from the first memory device,   wherein the memory controller is configured to send a first command to the first memory device and receive first data according to a first timing scheme to access the first memory device, and send to the conversion circuit a second command and a packet that includes a third command as an encapsulated command, and receive second data from the conversion circuit according to the first timing scheme,   wherein the conversion circuit is configured to send the third command to the second memory device and receive third data according to a second timing scheme, the third command is based on the second command,   wherein the conversion circuit is further configured to generate and transmit a read wait signal to the memory controller when the second data is ready to be delivered.   
     
     
       21. The memory system of claim 20, wherein the read wait signal is activated after the second data is stored in a memory abstraction block of the conversion circuit, and the second data is based on the third data from the second memory device. 
     
     
       22. The memory system of claim 21, wherein the memory controller is further configured to transmit the second command in response to the activating of the read wait signal. 
     
     
       23. The memory system of claim 22, wherein the first memory device is configured to communicate with the memory controller using a first communication protocol based on the first timing scheme, and the second memory device is configured to communicate with the conversion circuit using a second communication protocol based on the second timing scheme. 
     
     
       24. The memory system of claim 23, wherein the second memory device is configured to communicate with the memory controller through the conversion circuit. 
     
     
       25. The memory system of claim 24, wherein the conversion circuit is further configured to receive other information from the memory controller in association with the second command. 
     
     
       26. The memory system of claim 25, wherein the first timing scheme is used for accessing a volatile memory, and the second timing scheme is used for accessing a non-volatile memory. 
     
     
       27. The memory system of claim 26, wherein a first latency of the first timing scheme is smaller than a second latency of the second timing scheme, where the first latency indicates time period between sending the second command and receiving the second data by the memory controller and the second latency indicates time period between sending the third command and receiving the third data by the conversion circuit. 
     
     
       28. The memory system of claim 27, wherein the first memory device operates based on a deterministic interface and the second memory device operates based on a nondeterministic interface. 
     
     
       29. The memory system of claim 28, wherein the memory controller is further configured to transmit a chip select signal to select one of the first memory device and the second memory device. 
     
     
       30. The memory system of claim 29, wherein at least one of the first memory device and the second memory device includes a three-dimensional memory array in which word-lines and/or bit-lines are shared between levels. 
     
     
       31. The memory system of claim 20, wherein the memory controller is further configured to send and receive at least one of identification code, error code, and attribute along with the second command and the second data. 
     
     
       32. The memory system of claim 31, wherein the at least one of identification code, error code, and attribute are used during accessing the second memory device. 
     
     
       33. The memory system of claim 32, wherein the at least one of identification code, error code, and attribute are received by the memory controller within a first latency that is deterministic, where the first latency indicates time period between sending the second command and receiving the at least one of identification code, error code, and attribute by the memory controller. 
     
     
       34. An electronic device comprising:
 a memory controller;   a first memory device coupled to the memory controller;   a second memory device coupled to the memory controller, the second memory device being a different type of memory from the first memory device; and   a conversion circuit between the memory controller and the second memory device,   wherein the memory controller is configured to:   send a first command and first data to the first memory device according to a first timing scheme to access the first memory device, and   send a second command and a packet to the conversion circuit according to the first timing scheme to access the second memory device, and   wherein the conversion circuit is configured to:   receive the second command and the packet, and access the second memory device based on the second command and the packet, and   wherein:   the packet includes a header code, a tail code, and additional information, and   the conversion circuit is configured to strip the header code and the tail code, and to access the second memory device using the additional information.   
     
     
       35. The electronic device of claim 34, wherein the conversion circuit is configured to access the second memory device based on the second command and the packet according to a second timing scheme different from the first timing scheme. 
     
     
       36. The electronic device of claim 35, wherein the first memory device is configured to communicate directly with the memory controller using a first communication protocol that employs the first timing scheme, and the second memory device is configured to communicate with the memory controller through the conversion circuit using a second communication protocol that employs the second timing scheme. 
     
     
       37. The electronic device of claim 35, wherein the first timing scheme is a timing scheme used for accessing a volatile memory, and the second timing scheme is a timing scheme used for accessing a non-volatile memory. 
     
     
       38. The electronic device of claim 34, wherein the memory controller is further configured to transmit a chip select signal that selects one of the first memory device and the second memory device. 
     
     
       39. The electronic device of claim 34, wherein at least one of the first memory device and the second memory device includes a three-dimensional memory array in which word-lines and/or bit-lines are shared between levels.