Nonvolatile memory device, memory system including the same and method of operating the same

Abstract

A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.

What is claimed is: 
     
       1. A nonvolatile memory device comprising:
 a first memory structure including first through N-th memory dies configured to be connected to an external memory controller via a first channel, where N is a natural number equal to or greater than two, 
 at least one of the first through N-th memory dies being configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for a different one of the first through N-th memory dies rather than the first representative die, 
 wherein the first representative die is configured to enter an ODT mode to perform the ODT operation instead of the data write operation if a data write command is received from the external memory controller via the first channel and the different one of the first through N-th memory dies is a target die for the data write operation. 
 
     
     
       2. The nonvolatile memory device of  claim 1 , wherein
 the first through N-th memory dies are configured to commonly receive a first chip enable signal from the external memory controller, and 
 the first memory structure is configured to perform the data write operation and the ODT operation if first chip enable signal is activated. 
 
     
     
       3. A The nonvolatile memory device comprising: of claim 1, wherein
 a first memory structure including first through N-th memory dies configured to be connected to an external memory controller via a first channel, where N is a natural number equal to or greater than two, 
 at least one of the first through N-th memory dies being configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies, 
 wherein the first representative die is configured to enter an ODT mode to perform the ODT operation if a data write command is received from the external memory controller via the first channel, 
 each of the first through N-th memory dies is configured to receive a respective one of first through N-th chip enable signals from the external memory controller, 
 the first memory structure is configured to perform the data write operation for a K-th memory die if a K-th chip enable signal is activated, 
 K is a natural number equal to or less than N, and equal to or greater than one, 
 the first memory structure is configured to perform the ODT operation if an Lth chip enable signal is activated, 
 L is a natural number equal to or less than N, and equal to or greater than one, 
 an L-th memory die is the at least one of the first through N-th memory dies configured to be used as the first representative die, and 
 the L-th memory die is configured to perform the ODT operation based on the activated L-th chip enable signal. 
 
     
     
       4. The nonvolatile memory device of  claim 1 , wherein the first representative die is configured to exit the ODT mode when a data write completion command is received from the external memory controller via the first channel after the data write operation is performed based on the data write command. 
     
     
       5. The nonvolatile memory device of  claim 1 , wherein
 the first through N-th memory dies are configured to commonly receive a first ODT control signal from the external memory controller, and 
 the first representative die is configured to enter an the ODT mode and perform the ODT operation when a the data write command is received from the external memory controller via the first channel, and when the first ODT control signal is activated. 
 
     
     
       6. The nonvolatile memory device of  claim 1 , wherein the first through N-th memory dies are sequentially stacked on one another. 
     
     
       7. The nonvolatile memory device of  claim 6 , wherein
 each of the first through N-th memory dies includes input/output (I/O) pads arranged near one side of each memory die, 
 the first through N-th memory dies are stacked in a step shape such that the I/O pads of each memory chip are exposed, and 
 the first through N-th memory dies are electrically connected to one another via the I/O pads. 
 
     
     
       8. The nonvolatile memory device of  claim 6 , wherein
 each of the first through N-th memory dies includes through silicon vias (TSVs), and 
 the first through N-th memory dies are electrically connected to one another via the TSVs. 
 
     
     
       9. The nonvolatile memory device of  claim 1 , wherein the first representative die is configured to perform the ODT operation while a data read operation is performed for an other one of the first through N-th memory dies. 
     
     
       10. The nonvolatile memory device of  claim 1 , further comprising:
 a second memory structure including (N+1)-th through 2N-th memory dies connected to the external memory controller via the first channel, wherein 
 at least one of the (N+1)-th through 2N-th memory dies is configured to be used as a second representative die that performs that ODT operation while the data write operation is performed. 
 
     
     
       11. The nonvolatile memory device of  claim 10 , wherein the first representative die and the second representative die are configured to enter the ODT mode to perform the ODT operation when the data write command is received from the external memory controller via the first channel. 
     
     
       12. The nonvolatile memory device of  claim 11 , wherein
 the first through N-th memory dies are configured to commonly receive a first chip enable signal from the external memory controller, 
 the (N+1)-th through 2N-th memory dies are configured to commonly receive a second chip enable signal from the external memory controller, 
 the target die for the data write operation includes a first target die and a second target die, 
 the first target die is the different one of the first through N-th memory dies, 
 the second target die is one of the (N+1)-th through 2N-th memory dies, 
 the first target die and the second target die are configured to perform the data write operation and the first and second representative dies are configured to perform the ODT operation when the first chip enable signal and the second chip enable signal are activated. 
 
     
     
       13. The nonvolatile memory device of  claim 11 , wherein
 each of the first through N-th memory dies is configured to receive a respective one of first through N-th chip enable signals from the external memory controller, 
 each of the (N+1)-th through 2N-th memory dies is configured to receive a respective one of the first through N-th chip enable signals from the external memory controller, 
 the first memory structure is configured to perform the data write operation for a K-th memory die if a K-th chip enable signal is activated, 
 K is a natural number equal to or less than one and equal to or greater than N, 
 the first memory structure and the second memory structure are configured to perform the ODT operation if an I-th chip enable signal and a (J−N)-th chip enable signal are activated, 
 I is a natural number equal to or less than one and equal to or greater than N, 
 J is a natural number equal to or less than (N+1) and equal to or greater than 2N, 
 an I-th memory die is the at least one of the first through N-th memory dies configured to be used as the first representative die and a J-th memory die is the at least one of the (N+1)-th through 2N-th memory dies configured to be used as the second representative die, and 
 the I-th memory die and the J-th memory die are configured to perform the ODT operation based on the activated I-th and (J−N)-th chip enable signals, respectively. 
 
     
     
       14. The nonvolatile memory device of  claim 11 , wherein
 each of the first through N-th memory dies is configured to receive a respective one of first through N-th chip enable signals from the external memory controller, 
 each of the (N+1)-th through 2N-th memory dies is configured to receive a respective one of (N+1)-th through 2N-th chip enable signals from the external memory controller, 
 a K-th chip enable signal is activated to perform the data write operation for a K-th memory die, where K is a natural number equal to or less than one and equal to or greater than N, 
 an I-th chip enable signal and a J-th chip enable signal are activated to perform the ODT operation, where I is a natural number equal to or less than one and equal to or greater than N, where and J is a natural number equal to or less than (N+1) and equal to or greater than 2N, 
 an I-th memory die is configured to be used as the first representative die and a J-th memory die is configured to be used as the second representative die perform the ODT operation based on the activated I-th and J-th chip enable signals, respectively. 
 
     
     
       15. The nonvolatile memory device of  claim 10 , wherein
 the first through 2N-th memory dies are configured to commonly receive a first ODT control signal from the external memory controller, and 
 the first representative die and the second representative die are configured to enter an the ODT mode to perform the ODT operation when a the data write command is received from the external memory controller via the first channel, and when the first ODT control signal is activated. 
 
     
     
       16. The nonvolatile memory device of  claim 10 , wherein
 the first through N-th memory dies are configured to commonly receive a first ODT control signal from the external memory controller, 
 the (N+1)-th through 2N-th memory dies are configured to commonly receive a second ODT control signal from the external memory controller, and 
 the first representative die and the second representative die are configured to enter an the ODT mode to perform the ODT operation when a the data write command is received from the external memory controller via the first channel, and when the first ODT control signal and the second ODT control signal are activated. 
 
     
     
       17. A memory system comprising:
 the nonvolatile memory device of  claim 1 ; and 
 a memory controller, wherein 
 the memory controller is the external memory controller, 
 the nonvolatile memory device is a first nonvolatile memory device, 
 the first nonvolatile memory device is configured to be controlled by the memory controller such that the first memory structure includes the first through N-th memory dies and the first through N-th memory dies are connected to the memory controller via the first channel, 
 the first representative die is configured to perform the ODT operation while a data read operation is performed for an other one of the first through N-th memory dies. 
 
     
     
       18. The memory system of  claim 17 , further comprising:
 a second nonvolatile memory device configured to be controlled by the memory controller, the second nonvolatile memory device including a second memory structure, the second memory structure including first through M-th memory dies connected to the memory controller via the first channel, M being a natural number equal to or greater than two, 
 at least one of the first through M-th memory dies in the second memory structure being configured to be used as a second representative die that performs the ODT operation while the data write operation is performed. 
 
     
     
       19. A method of operating a nonvolatile memory device including a first memory structure including first through N-th memory dies configured to be connected to an external memory controller via a first channel, where N is a natural number equal to or greater than two, the method comprising:
 performing a data write operation or a data read operation for one of the first through N-th memory dies; and 
 performing an on-die termination (ODT) operation while the data write operation or the data read operation is performed, the performing the ODT operation including using at least one of the first through N-th memory dies as a first representative die to perform the ODT operation while the data write operation or the data read operation is performed on a different one of the first through N-th memory dies rather the first representative die, the first representative die being configured to enter an ODT mode to perform the ODT operation in response to receiving a data write command from the external memory controller via the first channel and the different one of the first through N-th memory dies being a target die for the data write operation. 
 
     
     
       20. The nonvolatile memory device of claim 1, wherein the external memory controller is configured to generate a setting signal for setting one of the first through N-th memory dies to the first representative die. 
     
     
       21. A nonvolatile memory device comprising:
 a first memory structure including first through N-th memory dies connected to an external memory controller via a first channel, where N is a natural number greater than or equal to two,   wherein at least one of the first through N-th memory dies in the first memory structure is designated as a first representative die that performs an on-die termination (ODT) operation while a first data write operation is performed for a different one of the first through N-th memory dies rather than the first representative die,   wherein the first representative die is configured to turn on an ODT mode to perform the ODT operation when an ODT control signal received through an ODT pin is activated regardless of chip selection, and the first representative die enters the ODT mode to perform the ODT operation instead of the first data write operation when the first memory structure receives a first data write command from the external memory controller via the first channel and the different one of the first through N-th memory dies is a target die for the first data write operation.   
     
     
       22. The nonvolatile memory device of claim 21, wherein the ODT control signal is shared by the first through N-th memory dies in the first memory structure. 
     
     
       23. The nonvolatile memory device of claim 21, wherein the ODT control signal is different from a command signal received through a command pin and an address signal received through an address pin. 
     
     
       24. The nonvolatile memory device of claim 21, wherein
 the ODT operation performed by the first representative die is an other-termination operation.   
     
     
       25. The nonvolatile memory device of claim 21, wherein the first through N-th memory dies are sequentially stacked on one another. 
     
     
       26. The nonvolatile memory device of claim 25, wherein
 each of the first through N-th memory dies includes input/output (I/O) pads arranged near one side of each memory die,   the first through N-th memory dies are stacked in a step shape such that the I/O pads of each memory chip are exposed, and   the first through N-th memory dies are electrically connected to one another via the I/O pads and bonding wires.   
     
     
       27. The nonvolatile memory device of claim 25, wherein
 each of the first through N-th memory dies includes through silicon vias (TSVs), and   the first through N-th memory dies are electrically connected to one another via the TSVs.   
     
     
       28. The nonvolatile memory device of claim 21, wherein each of all of the first through N-th memory dies includes an ODT circuit. 
     
     
       29. The nonvolatile memory device of claim 28, wherein the ODT circuit includes:
 a pull-up unit including a first switch and a first termination resistor that are connected in series between a first power supply voltage and a first node; and   a pull-down unit including a second switch and a second termination resistor that are connected in series between a second power supply voltage and the first node, the second power supply voltage being different from the first power supply voltage, and   wherein the first node is connected to an I/O pad, an input terminal of an input buffer and an output terminal of an output buffer.   
     
     
       30. The nonvolatile memory device of claim 28, wherein the ODT circuit includes:
 a pull-up unit including a third switch and a third termination resistor that are connected in series between a first power supply voltage and a first node, and   wherein the first node is connected to an I/O pad, an input terminal of an input buffer and an output terminal of an output buffer.   
     
     
       31. The nonvolatile memory device of claim 30, wherein the ODT circuit includes:
 a pull-down unit including a fourth switch and a fourth termination resistor that are connected in series between a second power supply voltage and a first node, and   wherein the first node is connected to an I/O pad, an input terminal of an input buffer and an output terminal of an output buffer.   
     
     
       32. The nonvolatile memory device of claim 21, wherein the first through N-th memory dies are configured to commonly receive a first chip enable signal from the external memory controller. 
     
     
       33. The nonvolatile memory device of claim 21, wherein each of the first through N-th memory dies is configured to receive a respective one of first through N-th chip enable signals from the external memory controller. 
     
     
       34. A nonvolatile memory device comprising:
 a first memory structure including first through N-th memory dies connected to an external memory controller via a first channel, where N is a natural number greater than or equal to two,   wherein at least one of the first through N-th memory dies in the first memory structure is designated as a first representative die that performs an on-die termination (ODT) operation while a first data write operation is performed for a different one of the first through N-th memory dies rather than the first representative die,   wherein all the first through N-th memory dies are configured to perform the ODT operation when an ODT control signal received through an ODT pin is activated, and the first representative die enters an ODT mode to perform the ODT operation instead of the first data write operation when the first memory structure receives a first data write command from the external memory controller via the first channel and the different one of the first through N-th memory dies is a target die for the data write operation,   wherein the first representative die is configured to perform the ODT operation while the first data write operation is performed for the target die, and   the target die is another of the first through N-th memory dies.   
     
     
       35. The nonvolatile memory device of claim 34, wherein the first through N-th memory dies are sequentially stacked on one another. 
     
     
       36. A storage device comprising:
 a memory controller; and   at least one nonvolatile memory device controlled by the memory controller, the nonvolatile memory device comprising:   a first memory structure including first through N-th memory chips connected to the memory controller via a first channel, where N is a natural number greater than or equal to two,   wherein at least one of the first through N-th memory chips in the first memory structure is designated as a first representative chip that performs an on-die termination operation (ODT) while a first data write operation is performed for a different one of the first through N-th memory chips rather than the first representative chip,   wherein the first representative chip is configured to turn on an ODT mode to perform the ODT operation when an ODT control signal received through an ODT pin is activated regardless of chip selection, and the first representative chip enters the ODT mode to perform the ODT operation instead of the first data write operation when the first memory structure receives a first data write command from the memory controller via the first channel and the different one of the first through N-th memory chips is a target chip for the first data write operation.