Capacitor device, organic light emitting display apparatus including the capacitor device, and method of manufacturing the organic light emitting display apparatus

Abstract

A capacitor device includes two top capacitor electrodes separated from each other and symmetrical to each other, two intermediate capacitor electrodes symmetrical to each other and respectively overlapping the top capacitor electrodes, a bridge coupling the intermediate capacitor electrodes without overlapping the top capacitor electrodes, and a driving voltage line coupled to the bridge and configured to apply a common voltage to the intermediate capacitor electrodes.

What is claimed is: 
     
       1. An organic light emitting display apparatus comprising:
 two pixels symmetrical to each other, located on a substrate, and adjacent each other in a first direction, each of the pixels comprising a pixel circuit and an organic light emitting diode (OLED);   two top capacitor electrodes separated from each other and symmetrical to each other, each of the top capacitor electrodes being respectively located in one of the pixel circuits;   two intermediate capacitor electrodes symmetrical to each other and insulated from, and overlapping with, the top capacitor electrodes;   a bridge coupling the intermediate capacitor electrodes without overlapping the top capacitor electrodes; and   a driving voltage line coupled to the bridge, and configured to apply a common voltage to the intermediate capacitor electrodes.   
     
     
       2. The organic light emitting display apparatus of  claim 1 , wherein an entirety of each of the top capacitor electrodes overlaps with a respective one of the intermediate capacitor electrodes. 
     
     
       3. The organic light emitting display apparatus of  claim 1 , further comprising two bottom capacitor electrodes symmetrical to each other and located below the intermediate capacitor electrodes, the bottom capacitor electrodes being insulated from, and overlapping with, the intermediate capacitor electrodes. 
     
     
       4. The organic light emitting display apparatus of  claim 3 , further comprising a contact node electrically coupling the bottom capacitor electrodes to each other, and electrically coupling the top capacitor electrodes to each other, via storage opening portions defined by the top capacitor electrodes, and by the intermediate capacitor electrodes, to expose the bottom capacitor electrodes. 
     
     
       5. The organic light emitting display apparatus of  claim 4 , wherein the contact node is configured to apply an initialization voltage during an initialization period. 
     
     
       6. The organic light emitting display apparatus of  claim 3 , further comprising a driving thin film transistor (TFT) comprising:
 a gate electrode that is the bottom capacitor electrodes; and   an active layer insulated from the bottom capacitor electrodes.   
     
     
       7. The organic light emitting display apparatus of  claim 1 , wherein the driving voltage line comprises:
 a plurality of first driving voltage lines extending in a second direction crossing the first direction and configured to apply the common voltage to the pixels; and   a second driving voltage line coupled to the bridge and extending in the first direction.   
     
     
       8. The organic light emitting display apparatus of  claim 7 , wherein the plurality of first driving voltage lines and the second driving voltage line comprise a mesh structure configuration. 
     
     
       9. The organic light emitting display apparatus of  claim 7 , wherein the first driving voltage lines are separated from one another and arranged symmetrically. 
     
     
       10. A display comprising:
 a first scanning line extending in a first direction;   a plurality of data lines extending in a second direction crossing the first direction; and   a plurality of pixel circuits arranged in a plurality of rows in the first direction and columns in the second direction and each comprising a plurality of transistors and a capacitor, the plurality of pixel circuits comprising a first pixel circuit and a second pixel circuit adjacent to each other in the first direction,   wherein each of the first pixel circuit and the second pixel circuit comprises:
 a first transistor electrically connected to the first scanning line and a respective data line of the plurality of data lines; 
 a second transistor electrically connected to the first transistor and comprising a first gate electrode and an active layer which is curved under the first gate electrode; and 
 a capacitor electrically connected to the second transistor and comprising a first capacitor electrode and a second capacitor electrode, and 
   wherein:
 the second capacitor electrode of the first pixel circuit overlaps a data line corresponding to the first pixel circuit, 
 the second capacitor electrode of the second pixel circuit overlaps a data line corresponding to the second pixel circuit, and 
 the second capacitor electrode of the first pixel circuit and the second capacitor electrode of the second pixel circuit are integrally coupled by a bridge which has a width less than a width of each of the second capacitor electrodes of the first and second pixel circuits. 
   
     
     
       11. The display of claim 10, wherein:
 the first gate electrode of the second transistor of the first pixel circuit comprises the first capacitor electrode of the capacitor of the first pixel circuit, and   the first gate electrode of the second transistor of the second pixel circuit comprises the first capacitor electrode of the capacitor of the second pixel circuit.   
     
     
       12. The display of claim 10, wherein each of the first pixel circuit and the second pixel circuit further comprises a third transistor electrically connected to the first scanning line and the second transistor. 
     
     
       13. The display of claim 12, wherein each of the third transistor of the first pixel circuit and the third transistor of the second pixel circuit comprises a gate electrode protruding from the first scanning line. 
     
     
       14. The display of claim 12, wherein:
 an active layer of the third transistor of the first pixel circuit is integrally coupled to the curved active layer of the second transistor of the first pixel circuit, and   an active layer of the third transistor of the second pixel circuit is integrally coupled to the curved active layer of the second transistor of the second pixel circuit.   
     
     
       15. The display of claim 12, wherein each of the first pixel circuit and the second pixel circuit further comprises a contact node that electrically connects the first gate electrode of the second transistor to the third transistor. 
     
     
       16. The display of claim 10, wherein each of the first pixel circuit and the second pixel circuit further comprises:
 a fourth transistor electrically connected to the second transistor; and   a driving voltage line electrically connected to the fourth transistor.   
     
     
       17. The display of claim 16, wherein each of the driving voltage line of the first pixel circuit and the driving voltage line of the second pixel circuit is electrically connected to an active layer of the fourth transistor via a contact hole in an insulation layer between the active layer of the fourth transistor and the driving voltage line. 
     
     
       18. A display comprising:
 a first scanning line extending in a first direction;   a plurality of data lines extending in a second direction crossing the first direction; and   a plurality of pixel circuits arranged in a plurality of rows in the first direction and columns in the second direction and each comprising a plurality of transistors and a capacitor, the plurality of pixel circuits comprising a first pixel circuit and a second pixel circuit adjacent to each other in the first direction,   wherein each of the first pixel circuit and the second pixel circuit comprises:
 a first transistor electrically connected to the first scanning line and a respective data line of the plurality of data lines; 
 a second transistor electrically connected to the first transistor and comprising a first gate electrode and an active layer which is curved under the first gate electrode; 
 a capacitor electrically connected to the second transistor and comprising a first capacitor electrode and a second capacitor electrode; and 
 a driving voltage line extending in the second direction, and 
   wherein the driving voltage line of the first pixel circuit and the driving voltage line of the second pixel circuit are integrally coupled by a coupling voltage line which extends in the first direction.   
     
     
       19. The display of claim 18, wherein the second capacitor electrode of the first pixel circuit and the second capacitor electrode of the second pixel circuit are integrally coupled by a bridge. 
     
     
       20. The display of claim 19, wherein a width of the bridge is less than a width of each of the second capacitor electrodes of the first and second pixel circuits. 
     
     
       21. The display of claim 19, wherein the driving voltage lines of the first and second pixel circuits, which are integrally coupled to each other, are electrically connected to the second capacitor electrodes of the first and second pixel circuits, which are integrally coupled to each other, at a first position. 
     
     
       22. The display of claim 21, wherein each of the first pixel circuit and the second pixel circuit further comprises a third transistor electrically connected to a second transistor, the third transistor being electrically connected to the driving voltage line at a second position, and
 wherein the second position is spaced apart from the first position.   
     
     
       23. The display of claim 22, wherein:
 an active layer of the third transistor of the first pixel circuit is integrally coupled to the curved active layer of the second transistor of the first pixel circuit, and   an active layer of the third transistor of the second pixel circuit is integrally coupled to the curved active layer of the second transistor of the second pixel circuit.   
     
     
       24. The display of claim 18, wherein:
 the second transistor of the first pixel circuit overlaps the capacitor of the first pixel circuit, and   the second transistor of the second pixel circuit overlaps the capacitor of the second pixel circuit.   
     
     
       25. The display of claim 24, wherein:
 the first gate electrode of the second transistor of the first pixel circuit comprises the first capacitor electrode of the capacitor of the first pixel circuit, and   the first gate electrode of the second transistor of the second pixel circuit comprises the first capacitor electrode of the capacitor of the second pixel circuit.   
     
     
       26. The display of claim 18, wherein each of the first pixel circuit and the second pixel circuit further comprises a fourth transistor electrically connected to the first scanning line and the second transistor. 
     
     
       27. The display of claim 26, wherein each of the fourth transistor of the first pixel circuit and the fourth transistor of the second pixel circuit comprises a gate electrode protruding from the first scanning line. 
     
     
       28. The display of claim 26, wherein:
 an active layer of the fourth transistor of the first pixel circuit is integrally coupled to the curved active layer of the second transistor of the first pixel circuit, and   an active layer of the fourth transistor of the second pixel circuit is integrally coupled to the curved active layer of the second transistor of the second pixel circuit.   
     
     
       29. A display comprising:
 a plurality of pixel circuits arranged in a plurality of rows in a first direction and columns in a second direction, the plurality of pixel circuits each comprising a plurality of transistors and a capacitor; and   a plurality of organic light emitting diodes electrically connected to the plurality of pixel circuits, respectively,   wherein two adjacent pixel circuits of the plurality of pixel circuits each comprises:
 a first transistor electrically connected to a first scanning line, which extends in the first direction, and a data line, which extends in the second direction; 
 a second transistor electrically connected to the first transistor and comprising a first gate electrode and an active layer which is curved under the first gate electrode; 
 a capacitor electrically connected to the second transistor and comprising a first capacitor electrode and a second capacitor electrode; and 
 a driving voltage line extending in the second direction, and 
   wherein the driving voltage line of a first one of the plurality of pixel circuits and the driving voltage line of a second one of the plurality of pixel circuits are integrally coupled to a coupling voltage line which extends in the first direction to form a mesh structure.