Semiconductor memory devices, memory systems including semiconductor memory devices, and operating methods of semiconductor memory devices

Abstract

A semiconductor memory device includes a memory core that performs reading and writing of data, data delivery and training blocks that are connected between first pads and the memory core, and at least one data delivery, clock generation and training block that is connected between at least one second pad and the memory core. In a first training operation, the data delivery and training blocks output first training data, received through the first pads, through the first pads as second training data. In a second training operation, at least one of the data delivery and training blocks outputs third training data, received through the at least one second pad, through at least one of the first pads as fourth training data. The second training data and the fourth training data are output in synchronization with read data strobe signals output through the at least one second pad.

What is claimed is: 
     
       1. A semiconductor memory device comprising:
 a memory core configured to perform reading and writing of data; 
 data delivery and training blocks connected between first pads and the memory core; and 
 at least one data delivery, clock generation and training block connected between at least one second pad and the memory core, 
 wherein, in a first training operation, the data delivery and training blocks output first training data, which are received through the first pads, through the first pads as second training data, 
 wherein, in a second training operation, at least one of the data delivery and training blocks outputs third training data, which are received through the at least one second pad, through at least one of the first pads as fourth training data, and 
 wherein the second training data and the fourth training data are output in synchronization with read data strobe signals output through the at least one second pad. 
 
     
     
       2. The semiconductor memory device of  claim 1 , wherein each of the data delivery and training blocks includes a first first-in first-out (FIFO) register,
 wherein the at least one data delivery, clock generation and training block includes a second FIFO register, and 
 wherein the first training operation and the second training operation are performed according to a FIFO register write command and a FIFO register read command. 
 
     
     
       3. The semiconductor memory device of  claim 2 , wherein, in the first training operation, the data delivery and training blocks store the first training data received from the first pads in respective first FIFO registers of the data delivery and training blocks responsive to the FIFO register write command, and
 wherein, in the first training operation, the data delivery and training blocks output the first training data stored in the first FIFO registers through the first pads as the second training data responsive to the FIFO register read command. 
 
     
     
       4. The semiconductor memory device of  claim 2 , wherein, in the second training operation, the at least one of the data delivery and training blocks stores the third training data received from the at least one second pad in at least one first FIFO register of the at least one of the data delivery and training blocks responsive to the FIFO register write command, and
 wherein, in the second training operation, the at least one of the data delivery and training blocks outputs the third training data stored in the at least one first FIFO register through the at least one of the first pads as the fourth training data responsive to the FIFO register read command. 
 
     
     
       5. The semiconductor memory device of  claim 2 , wherein the FIFO register write command comprises different respective options in the first training operation and the second training operation. 
     
     
       6. The semiconductor memory device of  claim 2 , wherein, in the second training operation, the at least one data delivery, clock generation and training block stores the third training data received from the at least one second pad in the second FIFO register responsive to the FIFO register write command, and
 wherein, in the second training operation, the at least one of the data delivery and training blocks outputs the third training data stored in the second FIFO register through the at least one of the first pads as the fourth training data responsive to the FIFO register read command. 
 
     
     
       7. The semiconductor memory device of  claim 2 , wherein, in the first training operation, the at least one data delivery, clock generation and training block stores the third training data received from the at least one second pad in the second FIFO register responsive to the FIFO register write command, and
 wherein, in the second training operation, the at least one of the data delivery and training blocks outputs the third training data stored in the second FIFO register through at least one of the first pads as the fourth training data responsive to the FIFO register read command. 
 
     
     
       8. The semiconductor memory device of  claim 2 , wherein the FIFO register read command comprises different respective options in the first training operation and the second training operation. 
     
     
       9. The semiconductor memory device of  claim 2 , wherein the memory core includes a mode register, and
 wherein the first training operation is selected responsive to the mode register being programmed to have a first option and the second training operation is selected responsive to the mode register being programmed to have a second option. 
 
     
     
       10. The semiconductor memory device of  claim 1 , wherein first data delivery and training blocks of the data delivery and training blocks transmit data bits, which are to be written in the memory core or are read from the memory core, between a first one of the first pads and the memory core. 
     
     
       11. The semiconductor memory device of  claim 10 , wherein the data bits include a data portion and a parity portion for the data portion. 
     
     
       12. The semiconductor memory device of  claim 10 , wherein the at least one data delivery, clock generation and training block transmits a write parity transmitted from the at least one second pad to the memory core and outputs at least one read data strobe signal through the at least one second pad. 
     
     
       13. The semiconductor memory device of  claim 10 , wherein second data delivery and training blocks of the data delivery and training blocks transmit data mask inversion signals, which are transmitted from a second one of the first pads, to the memory core and output a read parity transmitted from the memory core to the second one of the first pads. 
     
     
       14. The semiconductor memory device of  claim 1 , further comprising:
 at least one clock generation block connected to at least one third pad, 
 wherein the second training data and the fourth training data are output in synchronization with a second read data strobe signal output through the at least one third pad. 
 
     
     
       15. A memory system comprising:
 a semiconductor memory; and 
 a controller configured to control the semiconductor memory, 
 wherein the semiconductor memory and the controller communicate with each other through data input and output lines, data mask inversion lines, and read data strobe lines, 
 wherein, in a first training operation, the controller transmits first data to the semiconductor memory through the data input and output lines and the data mask inversion lines and reads the first data from the semiconductor memory through the data input and output lines and the data mask inversion lines, and 
 wherein, in a second training operation, the controller transmits second data to the semiconductor memory through the read data strobe lines and reads the second data from the semiconductor memory through at least two of the data input and output lines and the data mask inversion lines. 
 
     
     
       16. The memory system of  claim 15 , wherein the semiconductor memory outputs read data strobe signals through the read data strobe lines and outputs the first data and the second data through the data input and output lines and the data mask inversion lines in synchronization with the read data strobe signals. 
     
     
       17. The memory system of  claim 16 , wherein the controller transmits a clock signal to the semiconductor memory through a clock line and transmits a write clock signal to the semiconductor memory through a write clock line, and
 wherein the semiconductor memory adjusts the write clock signal to output the read data strobe signals. 
 
     
     
       18. The memory system of  claim 15 , wherein the controller selects one of the first training operation or the second training operation responsive to one of receiving a FIFO register write command, receiving a FIFO register read command, and a programming of a mode register. 
     
     
       19. A semiconductor memory device comprising:
 a memory core configured to perform reading and writing of data; 
 a first data delivery and training block connected between a first pad and the memory core; 
 a second data delivery and training block connected between a second pad and the memory core; and 
 a data delivery, clock generation and training block connected between a third pad and the memory core, 
 wherein, in a training input operation, the first and second data delivery and training blocks receive first and second training data through the first pad and the second pad, respectively, and the data delivery, clock generation and training block receives third training data through the third pad, 
 wherein, in a training output operation, the first data delivery and training block outputs the first training data through the first pad, and the second data delivery and training block combines the second and third training data to generate fourth training data and outputs the fourth training data through the second pad. 
 
     
     
       20. The semiconductor memory device of  claim 19 , wherein, in the training output operation, the data delivery, clock generation and training block outputs a read data strobe signal through the third pad, and
 wherein the first and second data delivery and training blocks respectively output the first and fourth training data in synchronization with the read data strobe signal. 
 
     
     
       21. A semiconductor memory device that is configured to perform a write training operation which comprises a first training operation and a second training operation, the semiconductor memory device comprising:
 a first data buffer coupled between a first pad and a first first-in first-out (FIFO) register, wherein the first data buffer, in response to a first FIFO register write command during the first training operation, is configured to receive a data mask inversion signal through the first pad and to store the received data mask inversion signal in the first FIFO register; and   a second data buffer coupled between a second pad and a second FIFO register, wherein the second data buffer, in response to a second FIFO register write command during the second training operation, is configured to receive a write parity signal through the second pad and to store the received write parity signal in the second FIFO register,   wherein the first data buffer, in response to a first FIFO register read command during the first training operation, is configured to output the data mask inversion signal stored in the first FIFO register through the first pad, and   wherein the first data buffer, in response to a second FIFO register read command during the second training operation, is configured to output the write parity signal stored in the second FIFO register through the first pad.   
     
     
       22. The semiconductor memory device of claim 21, wherein the second data buffer, in response to the first FIFO register read command during the first training operation, is configured to output a first read data strobe (RDQS) signal through the second pad, and
 wherein the second data buffer, in response to the second FIFO register read command during the second training operation, is configured to output a second RDQS signal through the second pad.   
     
     
       23. The semiconductor memory device of claim 22, wherein the first data buffer, in response to the first FIFO register read command during the first training operation, is configured to output the data mask inversion signal stored in the first FIFO register in synchronization with the first RDQS signal, and
 wherein the first data buffer, in response to the second FIFO register read command during the second training operation, is configured to output the write parity signal stored in the second FIFO register in synchronization with the second RDQS signal.   
     
     
       24. The semiconductor memory device of claim 23, further comprising a third data buffer coupled between a third pad and a third FIFO register, wherein the third data buffer, in response to the first FIFO register write command, is configured to receive a first data signal through the third pad and to store the received first data signal in the third FIFO register, and
 wherein, the third data buffer, in response to the first FIFO register read command, is configured to output the first data signal stored in the third FIFO register through the third pad.   
     
     
       25. The semiconductor memory device of claim 24, wherein the third data buffer, in response to the second FIFO register write command, is configured to receive a second data signal through the third pad and to store the received second data signal in the third FIFO register, and
 wherein, the third data buffer, in response to the second FIFO register read command, is configured to output the second data signal stored in the third FIFO register through the third pad.   
     
     
       26. The semiconductor memory device of claim 25, wherein each of the first to third data buffers, during the write training operation, is further configured to:
 receive a write clock signal through a fourth pad;   latch one or more of the data mask inversion signal, the write parity signal, and the first and second data signals based on a toggling of the write clock signal; and   store the latched one or more of the data mask inversion signal, the write parity signal, and the first and second data signals in the first to third FIFO registers respectively.   
     
     
       27. The semiconductor memory device of claim 26, wherein the first to third data buffers are configured to repeat the write training operation with adjusted phase relationships between the write clock signal and each of the data mask inversion signal, the write parity signal, and the first and second data signals. 
     
     
       28. The semiconductor memory device of claim 21, further comprising a mode register, the mode register configured to set one of the first training operation and the second training operation of the semiconductor memory device. 
     
     
       29. The semiconductor memory device of claim 28, wherein the first and second FIFO register write commands comprise information that sets one of the first training operation and the second training operation of the semiconductor memory device. 
     
     
       30. The semiconductor memory device of claim 28, wherein the first and second FIFO register read commands comprise information that sets one of the first training operation and the second training operation of the semiconductor memory device. 
     
     
       31. The semiconductor memory device of claim 21, wherein the write parity signal is a cyclic redundancy code (CRC). 
     
     
       32. The semiconductor memory device of claim 31, wherein the CRC is configured to detect an error in communication with an external device. 
     
     
       33. A method for performing a write training operation in a semiconductor memory device, the method comprising:
 receiving a first first-in first-out (FIFO) register write command;   receiving a data mask inversion signal associated with the first FIFO register write command through a first pad and storing the received data mask inversion signal in a first FIFO register coupled to the first pad;   receiving a first FIFO register read command;   outputting the data mask inversion signal stored in the first FIFO register through the first pad in response to the first FIFO register read command;   receiving a second FIFO register write command;   receiving a write parity signal associated with the second FIFO register write command through a second pad and storing the received write parity signal in a second FIFO register coupled to each of the first and second pads;   receiving a second FIFO register read command; and   outputting the write parity signal stored in the second FIFO register through the first pad in response to the second FIFO register read command.   
     
     
       34. The method of claim 33, further comprising outputting a first read data strobe (RDQS) signal through the second pad in response to the first FIFO register read command and outputting a second RDQS signal through the second pad in response to the second FIFO register read command. 
     
     
       35. The method of claim 34, wherein the semiconductor memory device is configured to output the data mask inversion signal stored in the first FIFO register in synchronization with the first RDQS signal in response to the first FIFO register read command, and to output the write parity signal stored in the second FIFO register in synchronization with the second RDQS signal in response to the second FIFO register read command. 
     
     
       36. The method of claim 35, further comprising:
 receiving a first data signal through a third pad in response to the first FIFO register write command;   storing the received first data signal in a third FIFO register coupled to the third pad; and   outputting the first data signal stored in the third FIFO register through the third pad in response to the first FIFO register read command.   
     
     
       37. The method of claim 36, further comprising:
 receiving a second data signal through the third pad in response to the second FIFO register write command;   storing the received second data signal in the third FIFO register; and   outputting the second data signal stored in the third FIFO register through the third pad in response to the second FIFO register read command.   
     
     
       38. The method of claim 37, further comprising:
 receiving a write clock signal through a fourth pad;   latching the data mask inversion signal and the first data signal in response to the first FIFO register write command;   latching the write parity signal and the second data signal in response to the second FIFO register write command; and   storing the latched data mask inversion signal, the latched write parity signal and the latched first and second data signals in the first to third FIFO registers respectively.   
     
     
       39. The method of claim 38, further comprising repeating the write training operation with adjusted phase relationships between the write clock signal and each of the data mask inversion signal, the write parity signal and the first and second data signals. 
     
     
       40. The method of claim 33, wherein the write parity signal is a cyclic redundancy code (CRC). 
     
     
       41. The method of claim 40, wherein the CRC is configured to detect an error in communication with an external device. 
     
     
       42. A memory system that is configured to perform a write training operation, the memory system comprising:
 a semiconductor memory device comprising a plurality of first-in first-out (FIFO) registers; and   a memory controller coupled to the semiconductor memory device, the memory controller configured to perform a first training operation and a second training operation,   wherein the first training operation comprises:
 transmitting a first FIFO register write command followed by transmitting a first write clock (WCK) through a write clock controller pad and transmitting a data mask inversion signal through a first controller pad, the data mask inversion signal being latched by the first WCK and stored in a first FIFO register of the semiconductor memory device; 
 transmitting a first FIFO register read command for receiving the stored data mask inversion signal through the first controller pad; and 
 comparing logic values of the transmitted data mask inversion signal and the received stored data mask inversion signal, 
   wherein the second training operation comprises:
 transmitting a second FIFO register write command followed by transmitting a second WCK through the write clock controller pad and transmitting a write parity signal through a second controller pad, the write parity signal being latched by the second WCK and stored in a second FIFO register of the semiconductor memory device; 
 transmitting a second FIFO register read command for receiving the stored write parity signal through the first controller pad; and 
 comparing logic values of the transmitted write parity signal and the received stored write parity signal, 
 wherein the memory controller is further configured to repeat the first and second training operations after adjusting respective phase relationships between the first WCK and the data mask inversion signal and between the second WCK and the write parity signal. 
   
     
     
       43. The memory system of claim 42, wherein the memory controller is further configured to receive a first read data strobe (RDQS) signal through the second controller pad while receiving the stored data mask inversion signal through the first controller pad and to receive a second RDQS signal through the second controller pad while receiving the stored write parity signal through the first controller pad. 
     
     
       44. The memory system of claim 43, wherein the stored data mask inversion signal and the stored write parity signal are received in synchronization with the first and second RDQS signals respectively. 
     
     
       45. The memory system of claim 44, wherein the memory controller is further configured to transmit a first data signal through a third controller pad after transmitting the first FIFO register write command for storing the first data signal in a third FIFO register of the semiconductor memory device and to receive the stored first data signal through the third controller pad after transmitting the first FIFO register read command. 
     
     
       46. The memory system of claim 45, wherein the memory controller is further configured to transmit a second data signal through the third controller pad after transmitting the second FIFO register write command for storing the second data signal in the third FIFO register of the semiconductor memory device and to receive the stored second data signal through the third controller pad after transmitting the second FIFO register read command. 
     
     
       47. The memory system of claim 42, wherein the memory controller is further configured to program a mode register of the semiconductor memory device to set one of the first training operation and the second training operation. 
     
     
       48. The memory system of claim 42, wherein the first and second FIFO register write commands comprise information that sets one of the first training operation and the second training operation. 
     
     
       49. The memory system of claim 42, wherein the write parity signal is a cyclic redundancy code (CRC), and
 wherein the CRC is configured to detect an error in communication between the memory controller and the semiconductor memory device.   
     
     
       50. A semiconductor memory device performing a write training operation which comprises a first training operation and a second training operation, the semiconductor memory device comprising:
 a first pad;   a first data buffer coupled to the first pad and configured to receive a data mask inversion signal through the first pad in response to a first first-in first-out (FIFO) register write command and output the received data mask inversion signal through the first pad in response to a first FIFO register read command during the first training operation;   a second pad; and   a second data buffer coupled to the second pad and configured to receive a write parity signal through the second pad in response to a second FIFO register write command and output a read data strobe (RDQS) signal through the second pad during the second training operation,   wherein the first data buffer is further configured to output the received write parity signal through the first pad in response to the second FIFO register read command during the second training operation.   
     
     
       51. The semiconductor memory device of claim 50, wherein the first data buffer, during the first training operation, stores the data mask inversion signal in a first FIFO register in response to the first FIFO register write command and outputs the stored data mask inversion signal through the first pad in response to the first FIFO register read command, and the second data buffer, during the second training operation, stores the write parity signal in a second FIFO register in response to the second FIFO register write command and outputs the stored write parity signal through the first pad in response to the second FIFO register read command. 
     
     
       52. The semiconductor memory device of claim 50, wherein the first data buffer, during the first training operation, stores the data mask inversion signal in a FIFO register in response to the first FIFO register write command and outputs the stored data mask inversion signal through the first pad in response to the first FIFO register read command, and the second data buffer, during the second training operation, stores the write parity signal in the FIFO register in response to the second FIFO register write command and outputs the stored write parity signal through the first pad in response to the second FIFO register read command. 
     
     
       53. The semiconductor memory device of claim 50, wherein the first data buffer, during the first training operation, outputs the received data mask inversion signal through the first pad in synchronization with a second RDQS signal output through the second pad, and the first data buffer, during the second training operation, outputs the received write parity signal through the first pad in synchronization with the RDQS signal output through the second pad. 
     
     
       54. The semiconductor memory device of claim 50, further comprising a third data buffer coupled to a third pad, wherein the third data buffer receives a first data signal through the third pad in response to the first FIFO register write command and outputs the received first data signal through the third pad in response to the first FIFO register read command. 
     
     
       55. The semiconductor memory device of claim 54, wherein the third data buffer stores the received first data signal in a third FIFO register. 
     
     
       56. The semiconductor memory device of claim 54, wherein, during the write training operation, each of the first to third data buffers receives a write clock signal through a fourth pad and latches each of the data mask inversion signal, write parity signal, and the first data signal by toggling the write clock signal and stores each latched signal in corresponding FIFO register respectively. 
     
     
       57. The semiconductor memory device of claim 50, wherein the semiconductor memory device repeats the write training operation with adjusted phase relationships between the write clock signal and each of the data mask inversion signal, write parity signal and the first data signal. 
     
     
       58. The semiconductor memory device of claim 50, further comprising a mode register, the mode register being programmed to set one of the first training operation and the second training operation of the semiconductor memory device. 
     
     
       59. The semiconductor memory device of claim 50, wherein the first and second FIFO register write commands include first information setting one of the first training operation and the second training operation of the semiconductor memory device, and the first and second FIFO register read commands include second information setting one of the first training operation and the second training operation of the semiconductor memory device. 
     
     
       60. The semiconductor memory device of claim 50, wherein the write parity signal is a cyclic redundancy code (CRC). 
     
     
       61. The semiconductor memory device of claim 60, wherein the CRC is used for detecting an error occurred while communicating with an external device. 
     
     
       62. A method for performing a write training operation in a semiconductor memory device, the method comprising:
 receiving a first first-in first-out (FIFO) register write command;   receiving a data mask inversion signal associated with the first FIFO register write command through a first pad;   receiving a first FIFO register read command;   outputting the received data mask inversion signal through the first pad in response to the first FIFO register read command;   receiving a second FIFO register write command;   receiving a write parity signal associated with the second FIFO register write command through a second pad;   receiving a second FIFO register read command; and   outputting the received write parity signal through the first pad in response to the second FIFO register read command,   wherein the received write parity signal is output through the first pad in synchronization with a read data strobe (RDQS) signal which is output through the second pad.   
     
     
       63. The method of claim 62, wherein the received data mask inversion signal is output through the first pad in synchronization with a second RDQS signal which is output through the second pad. 
     
     
       64. The method of claim 63, wherein the received data mask inversion signal is stored in a first FIFO register and the received write parity signal is stored in a second FIFO register. 
     
     
       65. The method of claim 64, further receiving a first data signal through a third pad in response to the first FIFO register write command and outputting the received first data signal stored through the third pad in response to the first FIFO register read command. 
     
     
       66. The method of claim 65, further receiving a second data signal through the third pad in response to the second FIFO register write command and outputting the received second data signal through the third pad in response to the second FIFO register read command. 
     
     
       67. The method of claim 66, further receiving a write clock signal through a fourth pad and latching the data mask inversion signal and the write parity signal respectively. 
     
     
       68. The method of claim 67, further repeating the whole steps with adjusted phase relationships between the write clock signal and each of the data mask inversion signal and the write parity signal. 
     
     
       69. The method of claim 62, wherein the received data mask inversion signal and the received write parity signal are stored in a FIFO register before outputting through the first pad.