Generation of fast frequency ramps

Abstract

A circuit includes an RF oscillator coupled in a phase-locked loop. The phase-locked loop is configured to receive a digital input signal, which is a sequence of digital words, and to generate a feedback signal for the RF oscillator based on the digital input signal. The circuit further includes a digital-to-analog conversion unit that includes a pre-processing stage configured to pre-process the sequence of digital words and a digital-to-analog-converter configured to convert the pre-processed sequence of digital words into the analog output signal. The circuit includes circuitry configured to combine the analog output signal and the feedback signal to generate a control signal for the RF oscillator. The pre-processing stage includes a word-length adaption unit configured to reduce the word-lengths of the digital words and a sigma-delta modulator coupled to the word-length adaption unit downstream thereof and configured to modulate the sequence of digital words having reduced word-lengths.

What is claimed is: 
     
       1. A phase locked loop (PLL) circuit comprising:
 a voltage-controlled oscillator configured to generate a radio frequency (RF) oscillator signal based on a control voltage;   a feedback loop configured to provide a feedback signal based on the RF oscillator signal, the feedback loop comprising a fractional-N frequency divider, a phase detector and a loop filter, wherein a division ratio of the fractional-N frequency divider is set based on a digital input signal, which is a sequence of digital words; and   a digital-to-analog conversion unit configured to receive the digital input signal and to generate an analog output signal, the digital-to-analog conversion unit comprising a pre-processing stage configured to pre-process the sequence of digital words, a digital-to-analog-converter configured to convert the pre-processed sequence of digital words into the analog output signal, and circuitry configured to combine the analog output signal and the feedback signal to generate the control voltage,   wherein the pre-processing stage includes a word-length adaption unit configured to generate the pre-processed sequence of digital words by reducing the word-lengths of the digital words in the sequence of digital words and further includes a sigma-delta modulator coupled to the word-length adaption unit downstream thereof, the sigma-delta modulator being configured to modulate the pre-processed sequence of digital words having reduced word-lengths and output the pre-processed sequence of digital words, as modulated, to the digital-to-analog-converter.   
     
     
       2. The PLL circuit of  claim 1 , wherein the digital-to-analog conversion unit further comprises a post-processing stage coupled to the digital-to-analog-converter downstream thereof. 
     
     
       3. The PLL circuit of  claim 2 , wherein the post-processing stage comprises at least a low-pass filter. 
     
     
       4. The PLL circuit of  claim 1 , wherein the digital-to-analog conversion unit is a current-steering digital-to-analog converter. 
     
     
       5. The PLL circuit of  claim 1 , wherein the pre-processing stage further comprises a decimator configured to reduce a clock rate of the sequence of digital words by a decimation factor. 
     
     
       6. The PLL circuit of  claim 1 , wherein the pre-processing stage further comprises a pre-distortion unit configured to pre-distort digital information included in the sequence of digital words to compensate for a non-linear characteristic of the voltage-controlled oscillator. 
     
     
       7. The PLL circuit of  claim 1 , wherein the digital-to-analog conversion unit has a control input receiving an adjustable gain value, and wherein the adjustable gain value is set by the word-length adaption unit. 
     
     
       8. The PLL circuit of  claim 1 , wherein the word-length adaption unit is configured to reduce the word-length of the digital words of the sequence of digital words by extracting, from the digital word and at a selectable bit position of the digital word, a digital word with reduced word-length. 
     
     
       9. The PLL circuit of  claim 8 , wherein the word-length adaption unit is further configured to set a gain of the digital-to-analog conversion unit depending on the bit position. 
     
     
       10. The PLL circuit of  claim 1 , wherein the circuitry configured to combine the analog output signal and the feedback signal is part of the loop filter. 
     
     
       11. The PLL circuit of  claim 10 , wherein the output of the digital-to-analog conversion unit is coupled to an integrator stage of the loop filter. 
     
     
       12. The PLL circuit of  claim 11 , wherein the integrator stage of the loop filter is coupled between an input of the loop filter and a reference circuit node, to which the analog output signal of the digital-to-analog conversion unit is supplied. 
     
     
       13. A method comprising:
 generating an RF oscillator signal using an RF oscillator that is coupled in a phase-locked loop, the phase-locked loop configured to generate a feedback signal for the RF oscillator based on a digital input signal, which is a sequence of digital words;   converting the digital input signal to an analog output signal, wherein the converting comprises reducing word-lengths of the digital words in the sequence of digital words, sigma-delta modulating the sequence of digital words having reduced word-lengths, and converting the modulated sequence of digital words of reduced word-lengths to obtain the analog output signal; and   combining the analog output signal and the feedback signal to generate a control signal for the RF oscillator.   
     
     
       14. The method of  claim 13 , further comprising:
 reducing a clock rate of the sequence of digital words by a decimation factor.   
     
     
       15. The method of  claim 13 , further comprising:
 pre-distorting digital information included in the sequence of digital words to compensate for a non-linear characteristic of the RF oscillator.   
     
     
       16. The method of  claim 13 , further comprising:
 filtering the analog output signal.   
     
     
       17. A circuit comprising:
 an RF oscillator coupled in a phase-locked loop, the phase-locked loop configured to receive a digital input signal, which is a sequence of digital words, and to generate an RF oscillator signal based on a control signal derived from the digital input signal, and generate a feedback signal for the RF oscillator based on the RF oscillator signal and the digital input signal; and 
 a digital-to-analog conversion unit configured to receive the digital input signal and to generate an analog output signal, the digital-to-analog conversion unit comprising a pre-processing stage configured to pre-process the sequence of digital words and a digital-to-analog-converter configured to convert the pre-processed sequence of digital words into the analog output signal, and circuitry configured to combine the analog output signal and the feedback signal to generate a control signal for the RF oscillator, 
 a compensation circuit comprising a pre-processing stage configured to receive and pre-process the sequence of digital words to generate an output signal, and circuitry configured to combine the output signal and the feedback signal to generate the control signal for the RF oscillator,  
 wherein the pre-processing stage includes a word-length adaption unit processing circuit configured to generate the pre-processed sequence of digital words by reducing the word-lengths of the digital words in the sequence of digital words and further includes a sigma-delta modulator coupled to the word-length adaption unit processing circuit downstream thereof, the sigma-delta modulator being configured to modulate the pre-processed sequence of sequence of digital words having reduced word-lengths and output the pre-processed sequence of digital words, as modulated, to the digital-to-analog-converter. 
 
     
     
       18. The circuit of  claim 17 , wherein the phase-locked loop comprises a feedback loop configured to receive an the RF oscillator signal and to provide the feedback signal based on the RF oscillator signal, the feedback loop comprising a fractional-N frequency divider configured to effect a division ratio, which is based on the digital input signal. 
     
     
       19. The circuit of  claim 18 , wherein the feedback loop further comprises a phase detector and a loop filter that provides the feedback signal at its output. 
     
     
       20. The circuit of  claim 18 , wherein the pre-processing stage further comprises a decimator configured to reduce a clock rate of the sequence of digital words by a decimation factor. 
     
     
       21. A circuit, comprising:
 a phase locked loop (PLL) configured to generate frequency modulated RF signals, the PLL comprising:
 a first loop path between a phase comparator and an RF output of the PLL, the first loop path comprising an RF oscillator; and 
 a multi-modulus divider arranged in a feedback loop of the PLL; 
   a first input to receive a digital input signal comprising a sequence of digital words related to frequency ramps of the frequency modulated RF signals;   a first control path coupled to the first input and the multi-modulus divider, the first control path comprising a first sigma-delta modulator configured to generate a control signal for the multi-modulus divider to alter a division ratio of the multi-modulus divider based on the sequence of digital words; and   a second control path coupled to the first input and the first loop path, the second control path comprising a pre-processing stage, the pre-processing stage comprising a pre-distortion processing circuit and a second sigma-delta modulator, wherein the pre-distortion processing circuit is configured to compensate for a non-linear characteristic of the RF oscillator.   
     
     
       22. The circuit of claim 21, wherein an output of the pre-distortion processing circuit is coupled to an input of the second sigma-delta modulator. 
     
     
       23. The circuit of claim 21, wherein the pre-processing stage comprises a word-length adaption processing circuit configured to reduce a word-length of the sequence of digital words. 
     
     
       24. The circuit of claim 23, wherein the word-length adaption processing circuit is configured to reduce the word-length of the digital words in the sequence of digital words by extracting reduced digital words having a reduced word-length from the digital words at a selectable bit position in the digital words. 
     
     
       25. The circuit of claim 23, wherein the word-length adaption processing circuit is configured to generate a processed sequence of digital words by reducing the word-lengths of the digital words in the sequence of digital words. 
     
     
       26. The circuit of claim 25, wherein the second sigma-delta modulator is configured to receive the processed sequence of digital words, modulate the processed sequence of digital words having reduced word-lengths, and output the processed sequence of digital words, as modulated. 
     
     
       27. The circuit of claim 26, wherein the RF oscillator is controlled based on the modulated processed sequence of digital words output by the second sigma-delta modulator. 
     
     
       28. The circuit of claim 25, wherein the pre-processing stage further comprises a decimator configured to reduce a clock rate of the processed sequence of digital words by a decimation factor. 
     
     
       29. The circuit of claim 21, wherein the pre-processing stage further comprises a decimator configured to reduce a clock rate of the sequence of digital words by a decimation factor. 
     
     
       30. The circuit of claim 21, wherein the second sigma-delta modulator is a multi-stage noise shaping (MASH) sigma-delta modulator. 
     
     
       31. A circuit, comprising:
 a phase locked loop (PLL) configured to generate frequency modulated RF signals, the PLL comprising:
 a first loop path between a phase comparator and an RF output of the PLL, the first loop path comprising an RF oscillator; and 
 a multi-modulus divider arranged in a feedback loop of the PLL; 
   a first input to receive a digital input signal comprising a sequence of digital words related to frequency ramps of the frequency modulated RF signals;   a first control path coupled to the first input and the multi-modulus divider, the first control path comprising a first sigma-delta modulator configured to generate a control signal for the multi-modulus divider to alter a division ratio of the multi-modulus divider based on the sequence of digital words; and   a second control path coupled to the first input and the first loop path, the second control path comprising a pre-processing stage, the pre-processing stage comprising a word-length adaption processing circuit configured to generate a processed sequence of digital words by reducing the word-lengths of the digital words in the sequence of digital words and comprising a pre-distortion processing circuit configured to compensate for a non-linear characteristic of the RF oscillator.   
     
     
       32. The circuit of claim 31, further comprising:
 a second sigma-delta modulator in the second control path, wherein the second sigma-delta modulator is configured to receive the processed sequence of digital words, modulate the processed sequence of digital words having reduced word-lengths and output the processed sequence of digital words, as modulated.   
     
     
       33. The circuit of claim 32, wherein the RF oscillator is controlled based on the modulated processed sequence of digital words output by the second sigma-delta modulator. 
     
     
       34. The circuit of claim 31, wherein the pre-processing stage further comprises a decimator configured to reduce a clock rate of the sequence of digital words or the processed sequence of digital words by a decimation factor. 
     
     
       35. The circuit of claim 31, wherein the word-length adaption processing circuit is configured to reduce the word-length of the digital words in the sequence of digital words by extracting reduced digital words having a reduced word-length from the digital words at a selectable bit position in the digital words.