Semiconductor device including polygon-shaped standard cell

Abstract

A semiconductor device including a standard cell for implementing a logic element includes a first active region and a second active region extending in a second direction on a substrate and spaced apart from each other in a first direction perpendicular to the second direction, gate electrodes intersecting the first active region and the second active region, and source regions and drain regions formed on the first and second active regions at both sides of each of the gate electrodes. A boundary of the standard cell has a polygonal shape, excluding a quadrilateral shape, when viewed in a plan view. As a result, an area of the standard cell may be reduced to reduce a size of the semiconductor device.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a standard cell for forming a logic element, the standard cell being provided from a cell library and including: 
 a first active region including a first PMOS region and a first NMOS region that are spaced apart from each other in a first direction and extend in a second direction on a substrate, the second direction being perpendicular to the first direction; 
 a second active region including a second PMOS region and a second NMOS region that extend in the second direction on the substrate and are spaced apart from each other in the first direction; 
 gate electrodes which intersect the first active region and the second active region in the first direction and are spaced apart from each other in the second direction; 
 first source regions and first drain regions formed on the first active region at both sides of each of the gate electrodes in the second direction; 
 second source regions and second drain regions formed on the second active region at both sides of each of the gate electrodes in the second direction; and 
 a first power line extending in the second direction between the first active region and the second active region when viewed in a plan view, 
 wherein a boundary of the standard cell has a polygonal shape, excluding a quadrilateral shape, when an entirety of the boundary viewed in the plan view. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the standard cell further comprises:
 a second power line extending in the second direction, the first active region including a first edge adjacent to the first power line and a second edge opposite to the first edge and adjacent to the second power line; and 
 a third power line extending in the second direction, the second active region including a first edge adjacent to the first power line and a second edge opposite to the first edge and adjacent to the third power line, 
 wherein the boundary of the standard cell overlaps with the first power line, the second power line, and the third power line. 
 
     
     
       3. The semiconductor device of  claim 2 , wherein the standard cell further comprises:
 a first region having a first quadrilateral shape and overlapping with the first power line, the second power line, and the third power line; and 
 a second region having a second quadrilateral shape and overlapping with the first power line and the third power line, 
 wherein the second region is in contact with the first region, and shares a sub-boundary with the first region. 
 
     
     
       4. The semiconductor device of  claim 3 , wherein the standard cell further comprises a third region having a third quadrilateral shape and overlapping with the first power line and the third power line,
 the first region includes a first edge which extends in the first direction, and a second edge which extends in the first direction and is opposite to the first edge, 
 the second region is in contact with the first edge of the first region, and 
 the third region is in contact with the second edge of the first region. 
 
     
     
       5. The semiconductor device of  claim 3 , wherein the standard cell further comprises a fourth region having a fourth quadrilateral shape and overlapping with the first power line and the second power line,
 the first region includes a first edge which extends in the first direction, and a second edge which extends in the first direction and is opposite to the first edge, 
 the second region is in contact with the first edge of the first region, and 
 the fourth region is in contact with the second edge of the first region. 
 
     
     
       6. The semiconductor device of  claim 3 , wherein the standard cell further comprises a fifth region having a fifth quadrilateral shape and overlapping with the first power line, the second power line, and the third power line,
 the second region includes a first edge which extends in the first direction, a second edge which extends in the first direction and is opposite to the first edge, 
 the first region is in contact with the first edge of the second region, and 
 the fifth region is in contact with the second edge of the second region. 
 
     
     
       7. The semiconductor device of  claim 2 , wherein the first PMOS region and the second PMOS region are adjacent to the first power line. 
     
     
       8. The semiconductor device of  claim 4 , wherein the standard cell further comprises:
 a third active region which extends adjacent to the third power line on the substrate, and includes a third PMOS region and a third NMOS region that extend in the second direction and are spaced apart from each other in the first direction, the gate electrodes further extending to intersect the third active region; 
 third source regions and third drain regions formed on the third active region at both sides of each of the gate electrodes in the second direction; and 
 a fourth power line extending in the second direction, 
 wherein the third active region includes a first edge which extends in the second direction adjacent to the third power line, and a second edge which is opposite to the first edge and extends in the second direction adjacent to the fourth power line, 
 the standard cell further comprises a sixth region having a sixth quadrilateral shape and overlapping with the third power line and the fourth power line, and 
 the sixth region is in contact with the first region. 
 
     
     
       9. The semiconductor device of  claim 8 , wherein the second NMOS region and the third NMOS region are adjacent to the third power line. 
     
     
       10. A semiconductor device comprising:
 a standard cell for forming a logic element, the standard cell being provided from a cell library and including: 
 an NMOS region and a PMOS region which are spaced apart from each other in a first direction and extend in a second direction on a substrate, the second direction being perpendicular to the first direction; 
 gate electrodes which intersect the NMOS region and the PMOS region in the first direction and are spaced apart from each other in the second direction; 
 source regions and drain regions formed on the NMOS region and the PMOS region at both sides of each of the gate electrodes in the second direction; 
 a first power line extending in the second direction adjacent to a first edge of the NMOS region; 
 a second power line extending in the second direction adjacent to a second edge of the PMOS region; 
 a first region having a first quadrilateral shape and overlapping with the first power line and the second power line; and 
 a second region having a second quadrilateral shape and overlapping with the second power line and the PMOS region, the second region not overlapping the first power line, 
 wherein a boundary of the standard cell has a polygonal shape excluding a quadrilateral shape. 
 
     
     
       11. The semiconductor device of  claim 10 , wherein the NMOS region and the PMOS region are disposed between the first power line and the second power line when viewed in a plan view. 
     
     
       12. The semiconductor device of  claim 11 , wherein the second region is in contact with the first region, and shares a sub-boundary with the first region. 
     
     
       13. The semiconductor device of  claim 12 , wherein the standard cell further comprises a third region having a third quadrilateral shape and overlapping with the second power line and the PMOS region,
 the first region includes a first edge being in contact with the second region and a second edge opposite to the first edge, and 
 the third region is in contact with the second edge of the first region. 
 
     
     
       14. The semiconductor device of  claim 12 , wherein the standard cell further comprises a fourth region having a fourth quadrilateral shape and overlapping with the first power line and the NMOS region,
 the first region includes a first edge being in contact with the second region and a second edge opposite to the first edge, and 
 the fourth region is in contact with the second edge of the first region. 
 
     
     
       15. The semiconductor device of  claim 12 , wherein the standard cell further comprises a fifth region having a fifth quadrilateral shape and overlapping with the first power line and the second power line,
 the second region includes a first edge being in contact with the first region and a second edge opposite to the first edge, and 
 the fifth region is in contact with the second edge of the second region. 
 
     
     
       16. An integrated circuit comprising:
 a cell which is provided from a cell library and defined on a semiconductor substrate and includes an outer boundary configurable to form a polygonal shape, the cell further including, within the outer boundary: 
 a first PMOS region and a first NMOS region that are spaced apart from each other in a first direction and extend in a second direction on a substrate, the first direction being perpendicular to the second direction; 
 a second PMOS region and a second NMOS region that are spaced apart from each other in the first direction and extend in the second direction on the substrate; 
 gate electrodes which are spaced apart from each other in the second direction and extend in the first direction, each of the gate electrodes overlying the first PMOS region, the first NMOS region, the second PMOS region and the second NMOS region; and 
 source regions and drain regions formed on the first PMOS region and the first NMOS region at both sides of each of the gate electrodes in the second direction, 
 wherein the outer boundary of the cell does not form a quadrilateral shape, when the outer boundary is viewed in a plan view. 
 
     
     
       17. The integrated circuit of  claim 16 , wherein the outer boundary of the cell includes at least five individual continuous sides connected to one another for forming the polygonal shape. 
     
     
       18. The integrated circuit of  claim 16 , wherein the cell comprises a plurality of regions included within the outer boundary, and
 each of the plurality of regions is in contact with a neighboring region, of the plurality of regions, along a sub-boundary which delineates each of the plurality of regions from the neighboring region. 
 
     
     
       19. The integrated circuit of  claim 18 , wherein the cell further comprises:
 a first power line extending in the second direction between the first PMOS region and the second PMOS region; 
 a second power line extending in the second direction at a first outer boundary of the first NMOS region; and 
 a third power line extending in the second direction at a second outer boundary of the second NMOS region. 
 
     
     
       20. The integrated circuit of  claim 19 , wherein the plurality of regions includes:
 a first region defined on a first area of the semiconductor substrate and having a first quadrilateral shape, the first region including, within a first sub-boundary of the first quadrilateral shape, the first PMOS region, the first NMOS region, the second PMOS region, the second NMOS region, the first power line, the second power line, and the third power line; and 
 a second region defined on a second area of the semiconductor substrate to share the first sub-boundary with the first region and having a second quadrilateral shape, the second region including, within a second sub-boundary of the second quadrilateral shape, the second PMOS region and the second NMOS region, the first power line, and the third power line. 
 
     
     
       21. The semiconductor device of claim 2, wherein a distance between the first and second power lines is different from a distance between the first and third power lines.  
     
     
       22. The semiconductor device of claim 1, wherein the standard cell further comprises at least one active fin pattern formed on the substrate.  
     
     
       23. The semiconductor device of claim 1, further comprising a conductive line extending in the first direction across the first power line.  
     
     
       24. The semiconductor device of claim 1, further comprising a gate contact formed within at least one of the first active region or the second active region.  
     
     
       25. A semiconductor device comprising:
 a first row comprising:
 a first active region including a first active sub-region and a second active sub-region that are spaced apart from each other in a first direction and extend in a second direction on a substrate, the second direction being perpendicular to the first direction; and 
 a first source region and a first drain region formed on the first active region at both sides of a first gate electrode in the second direction; 
   a second row comprising:
 a second active region including a third active sub-region and a fourth active sub-region that extend in the second direction on the substrate and are spaced apart from each other in the first direction; and 
 a second source region and a second drain region formed on the second active region at both sides of a second gate electrode in the second direction; 
 a first power line extending in the second direction between the first active region and the second active region, wherein the first power line is disposed between the second active sub-region and the third active sub-region; 
 a second power line extending in the second direction, wherein the second power line is adjacent to the first active sub-region; and 
 a third power line extending in the second direction, wherein the third power line is adjacent to the fourth active sub-region; 
   wherein a height of the first row is different from a height of the second row;   wherein at least one standard cell is placed over the first row and the second row.    
     
     
       26. The semiconductor device of claim 25, wherein the first active sub-region and the fourth active sub-region comprise a first type of transistor, and the second active sub-region and the third active sub-region comprise a second type of transistor.  
     
     
       27. The semiconductor device of claim 25, wherein the first active sub-region and the fourth active sub-region comprise NMOS, and the second active sub-region and the third active sub-region comprise PMOS.  
     
     
       28. The semiconductor device of claim 25, wherein the first active sub-region and the fourth active sub-region comprise PMOS, and the second active sub-region and the third active sub-region comprise NMOS.  
     
     
       29. The semiconductor device of claim 25, wherein the first gate electrode and the second gate electrode are connected to each other.  
     
     
       30. The semiconductor device of claim 25, wherein at least one of the first gate electrode or the second gate electrode intersects the first active region and the second active region in the first direction.  
     
     
       31. The semiconductor device of claim 25, wherein a first standard cell is placed on the first row and a second standard cell is placed on the second row.  
     
     
       32. The semiconductor device of claim 25, wherein power supplied through the first power line is provided to at least one of the first source region, the first drain region, the second source region and the second drain region.  
     
     
       33. The semiconductor device of claim 25, wherein a power voltage or a ground voltage is provided through the first power line.  
     
     
       34. The semiconductor device of claim 25, wherein the at least one standard cell further comprises at least one active fin pattern formed on the substrate.  
     
     
       35. The semiconductor device of claim 34, wherein the at least one active fin pattern comprises at least two active fin patterns, and
 wherein the at least two active fin patterns extend in the second direction and are spaced apart from each other in the first direction.    
     
     
       36. The semiconductor device of claim 34, wherein the at least one active fin pattern comprises at least two active fin patterns, and
 wherein an isolation layer is formed between the at least two active fin patterns.    
     
     
       37. The semiconductor device of claim 34, wherein at least one of the first gate electrode or the second gate electrode is formed on the at least one active fin pattern, extends in the first direction to intersect the at least one active fin pattern.  
     
     
       38. The semiconductor device of claim 25, further comprising a conductive line extending in the first direction across the first power line.  
     
     
       39. The semiconductor device of claim 25, wherein at least one of the first gate electrode or the second gate electrode intersects at least one of the first, second or third power lines.  
     
     
       40. The semiconductor device of claim 25, further comprising a gate contact formed within at least one of the first active region or the second active region.  
     
     
       41. The semiconductor device of claim 25, further comprising a gate insulating pattern formed under at least one of the first gate electrode or the second gate electrode, wherein the gate insulating pattern comprises a high-k dielectric material.  
     
     
       42. The semiconductor device of claim 25, wherein the at least one standard cell has a polygonal shape.  
     
     
       43. The semiconductor device of claim 25, further comprising a capping pattern formed to cover a top surface of at least one of the first gate electrode or the second gate electrode.  
     
     
       44. The semiconductor device of claim 25, wherein the first or second source/drain region comprises epitaxial patterns.  
     
     
       45. The semiconductor device of claim 25, wherein the at least one standard cell is a multi-height cell.  
     
     
       46. The semiconductor device of claim 25, wherein a width of the at least one standard cell is greater than a height of the at least one standard cell.  
     
     
       47. A semiconductor device comprising:
 a first row comprising a first active region including a first active sub-region and a second active sub-region that are spaced apart from each other in a first direction and extend in a second direction on a substrate, the second direction being perpendicular to the first direction;   a second row comprising a second active region including a third active sub-region and a fourth active sub-region that extend in the second direction on the substrate and are spaced apart from each other in the first direction; and   a gate electrode that extends in the first direction, and intersects the first active sub-region, the second active sub-region, the third active sub-region and the fourth active sub-region,   wherein a height of the first row is different from a height of the second row, and   wherein at least one standard cell is placed over the first row and the second row.    
     
     
       48. The semiconductor device of claim 47, wherein the first row further comprises a first source region and a first drain region formed on the first active region at both sides of a gate electrode, and the second row further comprises a second source region and a second drain region formed on the second active region at both sides of the gate electrode.  
     
     
       49. The semiconductor device of claim 47, further comprising:
 a first power line extending in the second direction between the first active region and the second active region, wherein the first power line is disposed between the second active sub-region and the third active sub-region;   a second power line extending in the second direction, wherein the second power line is adjacent to the first active sub-region; and   a third power line extending in the second direction, wherein the third power line is adjacent to the fourth active sub-region.    
     
     
       50. The semiconductor device of claim 49, wherein power supplied through the
 first power line is provided to a source/drain region.    
     
     
       51. The semiconductor device of claim 49, wherein a power voltage or a ground voltage is provided through the first power line.  
     
     
       52. The semiconductor device of claim 47, wherein the second row is in contact with the first row, and shares a boundary with the first row.  
     
     
       53. The semiconductor device of claim 47, wherein the first active region and the second active region are spaced apart from each other in the second direction.  
     
     
       54. The semiconductor device of claim 47, wherein a first standard cell is placed on the first row and a second standard cell is placed on the second row.  
     
     
       55. The semiconductor device of claim 47, further comprising at least one active fin pattern formed on the substrate.  
     
     
       56. The semiconductor device of claim 55, wherein the at least one active fin pattern comprises at least two active fin patterns, and
 wherein the at least two active fin patterns extend in the second direction and are spaced apart from each other in the first direction.    
     
     
       57. The semiconductor device of claim 55, wherein the at least one active fin pattern comprises at least two active fin patterns, and
 wherein an isolation layer is formed between the at least two active fin patterns.    
     
     
       58. The semiconductor device of claim 55, wherein a gate electrode is formed on the at least one active fin pattern, extends in the first direction to intersect the at least one active fin pattern.  
     
     
       59. A semiconductor device comprising:
 a first standard cell, a second standard cell and a third standard cell comprising:   a first row comprising a first active region and a second active region;   a second row comprising a third active region and a fourth active region;   a third row comprising a fifth active region and a sixth active region, wherein the first row, the second row, and the third row are spaced apart from each other in a first direction and extend in a second direction on a substrate;   a first power line extending in the second direction, wherein the first power line is disposed between the second active region and the third active region;   a second power line extending in the second direction, wherein the second power line is adjacent to the first active region; and   a third power line extending in the second direction, wherein the third power line is disposed between the fourth active region and the fifth active region;   wherein a distance between the first and second power lines is different from a distance between the first and third power lines,   wherein the first standard cell is a single-height standard cell, and   wherein the second standard cell is a multi-height standard cell.    
     
     
       60. The semiconductor device of claim 59, wherein the third standard cell is a multi-height standard cell.  
     
     
       61. The semiconductor device of claim 59, wherein the second standard cell comprises four active regions.  
     
     
       62. The semiconductor device of claim 59, wherein the second standard cell comprises three active regions.  
     
     
       63. The semiconductor device of claim 59, wherein the third standard cell comprises six active regions.  
     
     
       64. The semiconductor device of claim 59, wherein the first active region and the fourth active region comprise a first type of transistor, and the second active region and the third active region comprise a second type of transistor.