Negative capacitance fet device with reduced hysteresis window

Abstract

Provided is a negative capacitance FinFET device including a FinFET device including a gate stack, a drain electrode and a source electrode formed on a substrate and a ferroelectric negative capacitor connected to the gate stack of the FinFET device and having a negative capacitance. The FinFET device has an extension length (Lext) from a side-wall of the gate stack to the drain electrode or the source electrode and the extension length is set such that a size of a hysteresis window in the negative capacitance FinFET device is 1 V or less.

We claim: 
     
       1. A negative capacitance FinFET FET device comprising:
 a FinFET FET device including a fin, a gate stack on the fin, a drain electrode and a source electrode formed on a substrate, which are electrically connected to the fin on opposing sides of the gate stack; and 
 a ferroelectric negative capacitor connected to the gate stack of the FinFET FET device and having a negative capacitance, 
 wherein the FinFET FET device has an extension length (L ext ) from a side-wall of the gate stack to the drain electrode or the source electrode, and 
 the extension length is set such that a size of a hysteresis window in the negative capacitance FinFET FET device is in a range from 0.4 V to 1 V or less. 
 
     
     
       2. The negative capacitance FinFET FET device of  claim 1 , wherein the extension length is set to be in a range from 80 nm to 150 nm. 
     
     
       3. The negative capacitance FinFET FET device of  claim 1 , wherein the extension length is set to be in a range from 120 nm to 150 nm. 
     
     
       4. The negative capacitance FinFET FET device of  claim 3 , wherein the size of the hysteresis window in the negative capacitance FinFET FET device is from 0.4 V to 0.5 V. 
     
     
       5. The negative capacitance FinFET FET device of  claim 1 , wherein a subthreshold slope (SS) of the negative capacitance FinFET FET device is from 5 mV/decade to 60 mV/decade at room temperature. 
     
     
       6. The negative capacitance FinFET FET device of  claim 1 , wherein a subthreshold slope (SS) of the negative capacitance FinFET FET device is from 5 mV/decade to 20 mV/decade at room temperature. 
     
     
       7. The negative capacitance FinFET FET device of  claim 1 , wherein the ferroelectric negative capacitor includes:
 a substrate; 
 a first electrode layer formed on the substrate; 
 a ferroelectric layer formed on the first electrode layer; and 
 a second electrode layer formed on the ferroelectric layer. 
 
     
     
       8. The negative capacitance FinFET FET device of  claim 7 , wherein the first electrode layer and the second electrode layer include at least one of lantanium lanthanum strontium manganite (La 0.7 Sr 0.3 MnO 3 ; LSMO), gold (Au), gadolinium scandate (GdScO 3 ), strontium ruthenate (SrRuO 3 ), silicon (Si), polysilicon, copper (Cu), silver (Ag), molybdenum (Mo), nickel (Ni), platinum (Pt), titanium (Ti), tantalum (Ta), and ruthenium (Ru). 
     
     
       9. The negative capacitance FinFET FET device of  claim 7 , wherein the ferroelectric layer includes at least one of PVDF [poly(vinylidenefluoride)], P(VDF-TrFE) [poly(vinylidenefluoride-trifluoroethylene)], PZT (lead zirconate titanate), BTO (barium titanate), BLT (bismuth lanthanum titanate), SBT (strontium bismuth tantalate), SLT (near-stoichiometric lithium tantalate), silicon-doped hafnium oxide (Si-doped HfO 2 ), hafnium zirconium oxide (HfZrO 2 ), and PbZrTiO 3 . 
     
     
       10. A manufacturing method of a negative capacitance FinFET device, comprising:
 forming, on a substrate, a FinFET device including a gate stack, a drain electrode and a source electrode;   forming a ferroelectric negative capacitor having a negative capacitance; and   connecting the ferroelectric negative capacitor to the gate stack of the FinFET device,   wherein the FinFET device has an extension length (L ext ) from a side-wall of the gate stack to the drain electrode or the source electrode, and   the extension length is set such that a size of a hysteresis window in the negative capacitance FinFET device is 1 V or less.   
     
     
       11. The manufacturing method of  claim 10 ,
 wherein the extension length is set to be in a range from 80 nm to 150 nm.   
     
     
       12. The manufacturing method of  claim 10 ,
 wherein the extension length is set to be in a range from 120 nm to 150 nm.   
     
     
       13. The manufacturing method of  claim 12 ,
 wherein the size of the hysteresis window in the negative capacitance FinFET device is from 0.4 V to 0.5 V.   
     
     
       14. The manufacturing method of  claim 10 ,
 wherein a subthreshold slope (SS) of the negative capacitance FinFET device is from 5 mV/decade to 60 mV/decade at room temperature.   
     
     
       15. The manufacturing method of  claim 10 ,
 wherein a subthreshold slope (SS) of the negative capacitance FinFET device is from 5 mV/decade to 20 mV/decade at room temperature.   
     
     
       16. The manufacturing method of  claim 10 ,
 wherein the forming of a ferroelectric negative capacitor includes:   forming a substrate;   forming a first electrode layer on the substrate;   forming a ferroelectric layer on the first electrode layer; and   forming a second electrode layer on the ferroelectric layer.   
     
     
       17. The manufacturing method of  claim 16 ,
 wherein the first electrode layer and the second electrode layer include at least one of lantaniumstrontium manganite (La 0.7 Sr 0.3 MnO 3 ; LSMO), gold (Au), gadolinium scandate (GdScO 3 ), strontium ruthenate (SrRuO 3 ), silicon (Si), polysilicon, copper (Cu), silver (Ag), molybdenum (Mo), nickel (Ni), platinum (Pt), titanium (Ti), tantalum (Ta), and ruthenium (Ru).   
     
     
       18. The manufacturing method of  claim 16 ,
 wherein the ferroelectric layer includes at least one of PVDF [poly(vinylidenefluoride)], P(VDF-TrFE) [poly(vinylidenefluoride-trifluoroethylene)], PZT (lead zirconate titanate), BTO (barium titanate), BLT (bismuth lanthanum titanate), SBT (strontium bismuth tantalate), SLT (near-stoichiometric lithium tantalate), silicon-doped hafnium oxide (Si-doped HfO 2 ), hafnium zirconium oxide (HfZrO 2 ), and PbZrTiO 3 .   
     
     
       19. A negative capacitance FET device, comprising:
 a ferroelectric negative capacitor;   a gate electrically connected to the ferroelectric negative capacitor;   a source electrode and a drain electrode on opposing sides of the gate, respectively, wherein the gate is spaced apart from the source electrode or the drain electrode by a distance such that a size of a hysteresis window in the negative capacitance FET device is in a range from 0.4 V to 1 V; and   a fin, which is electrically connected to the source and drain electrodes, and extends from the source electrode to the drain electrode and opposite the gate.   
     
     
       20. The negative capacitance FET device of claim 19,
 wherein the ferroelectric negative capacitor comprises a first electrode layer, a second electrode layer, and a ferroelectric layer between the first and second electrode layers, and   wherein the gate is electrically connected to the first electrode layer of the ferroelectric negative capacitor.   
     
     
       21. The negative capacitance FET device of claim 20, wherein the first electrode layer and the second electrode layer include at least one of lanthanum strontium manganite (La 0.7 Sr 0.3 MnO 3 ; LSMO), gold (Au), gadolinium scandate (GdScO 3 ), strontium ruthenate (SrRuO 3 ), silicon (Si), polysilicon, copper (Cu), silver (Ag), molybdenum (Mo), nickel (Ni), platinum (Pt), titanium (Ti), tantalum (Ta), and ruthenium (Ru). 
     
     
       22. The negative capacitance FET device of claim 20, wherein the ferroelectric layer includes at least one of PVDF [poly(vinylidenefluoride)], P(VDF-TrFE) [poly(vinylidenefluoride-trifluoroethylene)], PZT (lead zirconate titanate), BTO (barium titanate), BLT (bismuth lanthanum titanate), SBT (strontium bismuth tantalate), SLT (near-stoichiometric lithium tantalate), silicon-doped hafnium oxide (Si-doped HfO 2 ), hafnium zirconium oxide (HfZrO 2 ), and PbZrTiO 3 . 
     
     
       23. The negative capacitance FET device of claim 19, wherein a subthreshold slope (SS) of the negative capacitance FET device is from 5 mV/decade to 60 mV/decade at room temperature. 
     
     
       24. The negative capacitance FET device of claim 19, wherein the hysteresis window in the negative capacitance FET device is from 0.4V to 0.5V. 
     
     
       25. The negative capacitance FET device of claim 19, wherein a driving voltage of the negative capacitance FET device is 0.5V or less. 
     
     
       26. A FET device, comprising:
 a semiconductor fin having a gate stack thereon, which is capacitively coupled to a ferroelectric layer that provides negative capacitance characteristics to the FET device; and   a source electrode and a drain electrode electrically connected to opposing ends of the semiconductor fin on opposing sides of the gate stack, said gate stack having a sidewall spaced apart from the source electrode or the drain electrode by a sufficient distance to yield a hysteresis window within an I D  versus V G  characteristic of the FET device, which is in a range from 0.4 V to 1 V, where I D  and V G  correspond to a drain current and a gate voltage in the FET device, respectively.   
     
     
       27. The FET device of claim 26, wherein the ferroelectric layer includes at least one of PVDF [poly(vinylidenefluoride)], P(VDF-TrFE) [poly(vinylidenefluoride-trifluoroethylene)], PZT (lead zirconate titanate), BTO (barium titanate), BLT (bismuth lanthanum titanate), SBT (strontium bismuth tantalate), SLT (near-stoichiometric lithium tantalate), silicon-doped hafnium oxide (Si-doped HfO 2 ), hafnium zirconium oxide (HfZrO 2 ), and PbZrTiO 3 . 
     
     
       28. The FET device of claim 26, wherein a subthreshold slope (SS) of the FET device is in a range from 5 mV/decade to 60 mV/decade at room temperature. 
     
     
       29. The FET device of claim 26, wherein a driving voltage of the FET device is 0.5V or less; and wherein the sidewall of the gate stack is spaced from the source electrode or the drain electrode by an extension length (L ext ) in a range from 80 nm to 150 nm.