Adaptive modulation scheme of MOSFET driver key parameters for improved voltage regulator efficiency and system reliability

Abstract

Systems and methods for adaptive modulation of MOSFET driver key parameters for improved voltage regulator efficiency and reliability in a voltage regulator may include a power stage. The power stage may include a high side switch including a high side gate, a peak voltage detection circuit, and a high side driver strength modulator circuit. The high side driver strength modulator circuit may determine a high side driver strength level. The high side driver strength modulator circuit may also connect a subset of the set of high side gate drivers to the high side gate based on the high side driver strength level. The high side driver strength modulator circuit may also disconnect a remaining subset of the set of high side gate drivers from the high side gate.

What is claimed is: 
     
       1. A voltage regulator, comprising:
 a power stage including:   a high side switch including a high side gate;   a peak voltage detection circuit coupled to the high side switch to provide a voltage stress level based on a high side output voltage of the high side switch;   a high side driver strength modulator circuit coupled to the peak voltage detection circuit configured to:
 determine a high side driver strength level for a set of high side gate drivers based on a load current level of the power stage and the voltage stress level; 
 connect a subset of the set of high side gate drivers to the high side gate based on the high side driver strength level; and 
 disconnect a remaining subset of the set of high side gate drivers from the high side gate; and 
   a dead-time management circuit configured to:
 adjust a programmable portion of a dead-time duration for the set of high side gate drivers and a set of low side gate drivers, the dead-time duration including the programmable portion of the dead-time duration and a dynamic portion of the dead-time duration proportional to a change in temperature of the power stage when the power stage is in an operating temperature region, wherein the programmable portion of the dead-time duration is adjusted to a low temperature duration value when the dead-time management circuit determines that a current temperature of the power stage is less than or equal to a low temperature region threshold, and wherein the programmable portion of the dead-time duration is adjusted to a high temperature duration value when the dead-time management circuit determines that the current temperature of the power stage is greater than or equal to a high temperature region threshold. 
   
     
     
       2. The voltage regulator of  claim 1 , wherein
 higher positive load current levels correlate to higher driver voltage levels and lower positive load current levels correlate to lower driver voltage levels, and wherein   higher magnitude negative load current levels correlate to higher driver voltage levels and lower magnitude negative load current levels correlate to lower driver voltage values.   
     
     
       3. The voltage regulator of  claim 1 , the power stage further comprising:
 a low side switch including a low side gate; and   a low side driver strength modulator circuit coupled to the peak voltage detection circuit configured to:   determine a low side driver strength level for the set of low side gate drivers based on the load current level of the power stage and the voltage stress level;   connect a subset of the set of low side gate drivers to the low side gate based on the low side driver strength level; and   disconnect a remaining subset of the set of low side gate drivers from the low side gate.   
     
     
       4. The voltage regulator of  claim 3 , wherein each of the high side switch and the low side switch is a metal-oxide-semiconductor-field-effect-transistors (MOSFETs). 
     
     
       5. The voltage regulator of  claim 3 , further comprising:
 a driver strength modulator circuit including:
 a source impedance modulator circuit; 
 a set of high side driver switches, each coupled between a corresponding high side gate driver of the set of high side gate drivers and the high side gate, wherein the connection of the subset of the set of high side gate drivers to the high side gate further comprises: 
 the source impedance modulator circuit configured to close a subset of the set of high side driver switches to connect the subset of the set of high side gate drivers to the high side gate; 
 a sink impedance modulator circuit; and 
 a set of low side driver switches, each coupled between a corresponding low side gate driver of the set of low side gate drivers and the low side gate, wherein the connection of the subset of the set of low side gate drivers to the low side gate further comprises: 
 the sink impedance modulator circuit configured to close a subset of the set of low side driver switches to connect the subset of the set of low side gate drivers to the low side gate. 
   
     
     
       6. The voltage regulator of  claim 5 , further comprising:
 a driver voltage optimizer circuit configured to adjust a driver voltage level for the set of high side gate drivers and the set of low side gate drivers.   
     
     
       7. The voltage regulator of  claim 6 , wherein the driver voltage optimizer circuit to adjust the driver voltage level is further configured to:
 reduce the driver voltage level when the driver voltage optimizer circuit determines that the load current level is less than or equal to a light load current threshold level; and   increase the driver voltage level when the driver voltage optimizer circuit determines that the load current level is greater than a heavy load condition threshold level.   
     
     
       8. A method comprising:
 providing, by a peak voltage detection circuit of a power stage of a voltage regulator, a voltage stress level based on a high side output voltage of a high side switch of the power stage;   determining, by a high side driver strength modulator circuit of the power stage, a high side driver strength level for a set of high side gate drivers of the power stage based on a load current level of the power stage and the voltage stress level;   connecting a subset of the set of high side gate drivers to a high side gate of the high side switch based on the high side driver strength level;   disconnecting a remaining subset of the set of high side gate drivers from the high side gate; and   adjusting, by a dead-time management circuit, a programmable portion of a dead-time duration for the set of high side gate drivers and a set of low side gate drivers, wherein the dead-time duration includes the programmable portion of the dead-time duration and a dynamic portion of the dead-time duration proportional to a change in temperature of the power stage when the power stage is in an operating temperature region, and wherein adjusting the programmable portion of the dead-time duration for the set of high side gate drivers and the set of low side gate drivers comprises:
 determining when a current temperature of the power stage is less than or equal to a low temperature region threshold; 
 in response to determining that the current temperature is less than or equal to the low temperature region threshold, adjusting the programmable portion of the dead-time duration for the set of high side gate drivers and the set of low side gate drivers to a low temperature duration value; 
 determining when the current temperature of the power stage is greater than or equal to a high temperature region threshold; and 
 in response to determining that the current temperature is greater than or equal to the high temperature region threshold, adjusting the programmable portion of the dead-time duration for the set of high side gate drivers and the set of low side gate drivers to a high temperature duration value. 
   
     
     
       9. The method of  claim 8 , wherein
 higher positive load current levels correlate to higher driver voltage levels and lower positive load current levels correlate to lower driver voltage levels, and wherein   higher magnitude negative load current levels correlate to higher driver voltage levels and lower magnitude negative load current levels correlate to lower driver voltage values.   
     
     
       10. The method of  claim 8 , further comprising:
 determining, by a low side driver strength modulator circuit of the power stage, a low side driver strength level for the set of low side gate drivers of the power stage based on the load current level of the power stage and the voltage stress level;   connecting a subset of the set of low side gate drivers to a low side gate of a low side switch based on the low side driver strength level; and   disconnecting a remaining subset of the set of low side gate drivers from the low side gate.   
     
     
       11. The method of  claim 10 , wherein each of the high side switch and the low side switch is a metal-oxide-semiconductor-field-effect-transistors (MOSFETs). 
     
     
       12. The method of  claim 10 , wherein connecting the subset of the set of high side gate drivers to the high side gate further comprises:
 closing, by a source impedance modulator circuit, a subset of a set of high side driver switches of the power stage to connect the subset of the set of high side gate drivers to the high side gate; and wherein connecting the subset of the set of low side gate drivers to the low side gate further comprises:   closing, by a sink impedance modulator circuit, a subset of a set of low side driver switches to connect the subset of the set of low side gate drivers to the low side gate.   
     
     
       13. The method of  claim 12 , further comprising:
 adjusting, by a driver voltage optimizer circuit, a driver voltage level for the set of high side gate drivers and the set of low side gate drivers.   
     
     
       14. The method of  claim 13 , wherein adjusting the driver voltage level further comprises:
 reducing the driver voltage level when the driver voltage optimizer circuit determines that the load current level is less than or equal to a light load current threshold level; and   increasing the driver voltage level when the driver voltage optimizer circuit determines that the load current level is greater than a heavy load condition threshold level.   
     
     
       15. A voltage regulator, comprising:
 a power stage including:
 a first power switch having a high side switch including a high side gate; 
 a current sense circuit coupled to the high side switch to monitor and report a load current level of the power stage; 
 a high side driver strength modulator circuit that is coupled to the current sense circuit and that is configured to:
 determine a high side driver strength level for a set of high side gate drivers based on the load current level of the power stage; 
 connect a subset of the set of high side gate drivers to the high side gate based on the high side driver strength level; and 
 disconnect a remaining subset of the set of high side gate drivers from the high side gate; and 
 
 a dead-time management circuit that is configured to:
 adjust a dead-time duration of the set of high side gate drivers to a first dead-time duration based on a first power stage temperature; and 
 adjust the dead-time duration of the set of high side gate drivers to a second dead-time duration that is different than the first dead-time duration based on a second power stage temperature that is greater than the first power stage temperature, 
 wherein the adjusting of the dead-time duration of the set of high side gate drivers prevents the first power switch from turning on when a second power switch that is complementary to the first power switch is turned on. 
 
   
     
     
       16. A voltage regulator, comprising:
 a power stage including:
 a first power switch having a high side switch including a high side gate; 
 a peak voltage detection circuit coupled to the high side switch to provide a voltage stress level of a high side output voltage of the high side switch; 
 a high side driver strength modulator circuit that is coupled to the peak voltage detection circuit and that is configured to:
 determine a high side driver strength level for a set of high side gate drivers based on the voltage stress level of the high side output voltage of the high side switch; 
 connect a subset of the set of high side gate drivers to the high side gate based on the high side driver strength level; and 
 disconnect a remaining subset of the set of high side gate drivers from the high side gate; and 
 
 a dead-time management circuit that is configured to:
 adjust a dead-time duration of the set of high side gate drivers to a first dead-time duration based on a first power stage temperature; and 
 adjust the dead-time duration of the set of high side gate drivers to a second dead-time duration that is different than the first dead-time duration based on a second power stage temperature that is greater than the first power stage temperature, 
 wherein the adjusting of the dead-time duration of the set of high side gate drivers prevents the first power switch from turning on when a second power switch that is complementary to the first power switch is turned on. 
 
   
     
     
       17. A voltage regulator, comprising:
 a first power switch;   a turn-on gate driver that is configured to turn on the first power switch;   a plurality of P-channel Metal Oxide Semiconductor (PMOS) devices coupling the turn-on gate driver to the first power switch;   a turn-off gate driver that is configured to turn off the first power switch;   a plurality of N-channel Metal Oxide Semiconductor (NMOS) devices coupling the turn-off gate driver to the first power switch;   a current sense device that is configured to monitor and report load current information associated with a power stage load current;   at least one driver strength modulator that is coupled to the current sense device, the plurality of PMOS devices, and the plurality of NMOS devices, wherein the at least one driver strength modulator is configured to turn on the first power switch by:
 determining, based on the load current information reported by the current sense device, a turn-on driver strength level for the turn-on gate driver; and 
 connecting the turn-on gate driver to the first power switch via at least a first subset of the plurality of PMOS devices that is based on the turn-on driver strength level, and 
 wherein the at least one driver strength modulator is configured to turn off the first power switch by:
 determining, based on the load current information reported by the current sense device, a turn-off driver strength level for the turn-off gate driver; and 
 connecting the turn-off gate driver to the first power switch via at least a first subset of the plurality of NMOS devices that is based on the turn-off driver strength level; and 
 
   a dead-time management device that is configured to:
 adjust a dead-time duration of the turn-on gate driver and the turn-off gate driver to a first dead-time duration based on a first power stage temperature; and 
 adjust the dead-time duration of the turn-on gate driver and the turn-off gate driver to a second dead-time duration that is different than the first dead-time duration based on a second power stage temperature that is greater than the first power stage temperature, 
 wherein the adjusting of the dead-time duration of the turn-on gate driver and the turn-off gate driver prevents the first power switch from turning on when a second power switch that is complementary to the first power switch is turned on. 
   
     
     
       18. The voltage regulator of claim 17, wherein the at least one driver strength modulator is configured to determine the turn-on driver strength level for the turn-on gate driver based on the load current information reported by the current sense device by accessing a load current information/turn-on driver strength level table that associates respective turn-on driver strength levels with respective load current information, and wherein the at least one driver strength modulator is configured to determine the turn-off driver strength level for the turn-off gate driver based on the load current information reported by the current sense device by accessing a load current information/turn-off driver strength level table that associates respective turn-off driver strength levels with respective load current information. 
     
     
       19. The voltage regulator of claim 17, wherein the plurality of PMOS devices include the first subset and a second subset, and wherein the at least one driver strength modulator is configured to turn on the first power switch by:
 connecting the turn-on gate driver to the first power switch via the first subset of the plurality of PMOS devices that is based on the turn-on driver strength level; and   disconnecting the turn-on gate driver from the first power switch via the second subset of the plurality of PMOS devices that is based on the turn-on driver strength level.   
     
     
       20. The voltage regulator of claim 17, wherein the plurality of NMOS devices include the first subset and a second subset, and wherein the at least one driver strength modulator is configured to turn off the first power switch by:
 connecting the turn-off gate driver to the first power switch via the first subset of the plurality of NMOS devices that is based on the turn-on driver strength level; and   disconnecting the turn-off gate driver from the first power switch via the second subset of the plurality of NMOS devices that is based on the turn-on driver strength level.   
     
     
       21. The voltage regulator of claim 17, wherein the plurality of PMOS device and the plurality of NMOS devices are provided by a plurality of respective PMOS device/NMOS device pairs. 
     
     
       22. A voltage regulator, comprising:
 a first power switch;   a turn-on gate driver that is configured to turn on the first power switch;   a plurality of PMOS devices coupling the turn-on gate driver to the first power switch;   a turn-off gate driver that is configured to turn off the first power switch;   a plurality of NMOS devices coupling the turn-off gate driver to the first power switch;   a voltage detection device that is configured to monitor and report voltage stress information associated with a peak voltage produced by the first power switch during switching operations;   at least one driver strength modulator that is coupled to the voltage detection device, the plurality of PMOS devices, and the plurality of NMOS devices, wherein the at least one driver strength modulator is configured to turn on the first power switch by:
 determining, based on the voltage stress information reported by the voltage detection device, a turn-on driver strength level for the turn-on gate driver; and 
 connecting the turn-on gate driver to the first power switch via at least a first subset of the plurality of PMOS devices that is based on the turn-on driver strength level, and 
 wherein the at least one driver strength modulator is configured to turn off the first power switch by:
 determining, based on the voltage stress information reported by the voltage detection device, a turn-off driver strength level for the turn-off gate driver; and 
 connecting the turn-off gate driver to the first power switch via at least a first subset of the plurality of NMOS devices that is based on the turn-off driver strength level; and 
 
   a dead-time management device that is configured to:
 adjust a dead-time duration of the turn-on gate driver and the turn-off gate driver to a first dead-time duration based on a first power stage temperature; and 
 adjust the dead-time duration of the turn-on gate driver and the turn-off gate driver to a second dead-time duration that is different than the first dead-time duration based on a second power stage temperature that is greater than the first power stage temperature, 
 wherein the adjusting of the dead-time duration of the turn-on gate driver and the turn-off gate driver prevents the first power switch from turning on when a second power switch that is complementary to the first power switch is turned on. 
   
     
     
       23. The voltage regulator of claim 22, wherein the at least one driver strength modulator is coupled to each of the plurality of PMOS devices by respective PMOS switch devices and is configured to close each respective PMOS switch device connected to that PMOS device to connect the turn-on gate driver to the first power switch via that PMOS device. 
     
     
       24. The voltage regulator of claim 22, wherein the plurality of PMOS devices include the first subset and a second subset, and wherein the at least one driver strength modulator is configured to turn on the first power switch by:
 connecting the turn-on gate driver to the first power switch via the first subset of the plurality of PMOS devices that is based on the turn-on driver strength level; and   disconnecting the turn-on gate driver from the first power switch via the second subset of the plurality of PMOS devices that is based on the turn-on driver strength level.   
     
     
       25. The voltage regulator of claim 22, wherein the plurality of NMOS devices include the first subset and a second subset, and wherein the at least one driver strength modulator is configured to turn off the first power switch by:
 connecting the turn-off gate driver to the first power switch via the first subset of the plurality of NMOS devices that is based on the turn-on driver strength level; and   disconnecting the turn-off gate driver from the first power switch via the second subset of the plurality of NMOS devices that is based on the turn-on driver strength level.   
     
     
       26. The voltage regulator of claim 22, wherein the plurality of PMOS device and the plurality of NMOS devices are provided by a plurality of respective PMOS device/NMOS device pairs.