Memory controller, storage device and method for adjusting a data input/output speed of the controller based on internal and external temperature information

Abstract

Provided herein may be a storage device and a method of operating the same. In a storage device for controlling operational performance depending on temperature, a memory controller configured to control a memory device may include an internal temperature sensing unit configured to generate an internal temperature information by sensing a temperature of the memory controller and a performance adjustment unit configured to receive an external temperature information from an external temperature sensing unit, and controlling operational performance of the memory controller using the internal temperature information and the external temperature information, wherein the external temperature information represents a temperature of the memory device.

What is claimed is: 
     
       1. A memory controller for controlling a memory device, the memory controller comprising:
 an internal temperature sensor configured to generate an internal temperature information by sensing a temperature of the memory controller; and 
 a performance adjuster configured to receive an external temperature information from an external temperature sensing unit, and controlling operational performance a data input/output speed of the memory controller using the an internal temperature information and the external temperature information, 
 wherein the external temperature information represents a temperature of the memory device, and  
 wherein the performance adjuster comprises:
 a correction value generator configured to generate a correction value based on the internal and external temperature information; 
 a performance adjustment determination circuit configured to generate an adjusted temperature information, in which the correction value is applied to the internal temperature information, to compare the adjusted temperature information with pre-stored critical temperature information and then to determine whether to adjust the operational performance data input/output speed of the memory controller based on a result of the comparing comparison; and 
 a correction value update controller configured to generate an update enable signal for updating the correction value, and to output the update enable signal when a number of erase-write cycles (EW cycles) of the memory device exceeds a threshold number. 
 
 
     
     
       2. The memory controller according to  claim 1 , wherein the correction value generator generates the correction value when power is supplied to the memory controller. 
     
     
       3. The memory controller according to  claim 1 , wherein the correction value is a difference value between the internal temperature information and the external temperature information. 
     
     
       4. The memory controller according to  claim 1 , wherein the performance adjustment determination circuit adjuster controls the operational performance data input/output speed by outputting a throttling signal for activating a throttling operation that adjusts the operational performance data input/output speed of the memory controller when a write request for the memory device is inputted and the adjusted temperature information is higher than the critical temperature information. 
     
     
       5. The memory controller according to  claim 4 , wherein the throttling operation is an operation of decreasing a the data input/output speed of the memory controller. 
     
     
       6. The memory controller according to  claim 4 , wherein:
 the memory controller is capable of simultaneously accessing a plurality of memory devices, and 
 the throttling operation is an operation of decreasing a number of memory devices that the memory controller simultaneously accesses. 
 
     
     
       7. The memory controller according to  claim 4 , wherein the throttling operation is an operation of decreasing a frequency of a timing signal or a clock signal that is inputted to the memory device. 
     
     
       8. The memory controller according to  claim 4 , wherein the throttling operation is an operation of activating performance adjuster activates a cooler disposed outside the memory controller while the throttling operation is activated. 
     
     
       9. The memory controller according to  claim 1 , wherein the correction value update controller outputs the update enable signal when the internal temperature information is changed changes to exceed a critical value. 
     
     
       10. The memory controller according to  claim 1 , wherein the correction value update controller outputs the update enable signal when a preset reference time has elapsed. 
     
     
       11. The memory controller according to  claim 10 , wherein the preset reference time is set based on Quality of Service (QoS) criteria of the memory device. 
     
     
       12. A storage device comprising:
 a plurality of memory devices; and  
 an external temperature sensor configured to generate an external temperature information by sensing a temperature of the respective memory device; and 
 a memory controller configured to:
 control the plurality of memory devices, and control operational performance a data input/output speed of the memory controller using an internal temperature information and the external temperature information, wherein the internal temperature information represents a temperature of the memory controller, 
 wherein the memory controller is configured to 
 generate a correction value representing a difference value between the internal temperature information and the external temperature information, 
 togenerate an adjusted temperature information in which the correction value is applied to the internal temperature informationand,  
 to updatingupdate the correction value when a number of erase-write cycles (EW cycles) of the memory device exceeds a threshold number, and 
 determine whether to adjust the data input/output speed of the memory controller based on the adjusted temperature information. 
 
 
     
     
       13. The storage device according to  claim 12 , wherein the memory controller is configured to generate generates the correction value representing a difference value between the internal temperature information and the external temperature information when the storage device boots, and wherein generates the adjusted temperature information is generated in which the correction value is applied to the internal temperature information at a time at which a write request for the plurality of memory devices is inputted. 
     
     
       14. The storage device according to  claim 13 , wherein the memory controller is configured to control operational performance the data input/output speed by comparing the adjusted temperature information with a pre-stored critical temperature information. 
     
     
       15. A method of operating a storage device, the storage device including a plurality of memory devices and a memory controller for controlling the memory devices, the method comprising:
 obtaining, when a write request for the plurality of memory devices is inputted, internal temperature information representing a temperature of the memory controller; 
 generating, when the storage device boots, a correction value based on the internal temperature information and an external temperature information representing a temperature of the respective memory devices; 
 generating an adjusted temperature information by applying the correction value to the internal temperature information; 
 adjusting operational performance a data input/output speed of the memory controller using the adjusted temperature information and a pre-stored critical temperature information; and 
 updating the correction value in response to an update enable signal which is generated when a number of erase-write cycles (EW cycles) of the memory device exceeds a threshold number. 
 
     
     
       16. The method according to  claim 15 , wherein the operational performance data input/output speed is adjusted when the adjusted temperature information exceeds the critical temperature information. 
     
     
       17. The method according to  claim 15 , further comprising generating an update enable signal when the internal temperature information is changed changes to exceed a critical value.