Methods of designing a layout of a semiconductor device including field effect transistor and methods of manufacturing a semiconductor device using the same

Abstract

A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.

What is claimed is: 
     
       1. A method of producing a layout of a semiconductor device, comprising:
 providing a standard cell layout, the providing of the standard cell layout comprising creating a preliminary pin pattern of an interconnection layout of the standard cell layout in association with a lower metal layer of the semiconductor device; 
 performing a routing step to produce a high-level interconnection layout in which a the preliminary pin pattern is connected to a high-level interconnection pattern, the high-level interconnection layout representative of an upper level metal interconnection of the semiconductor device disposed above the lower metal layer; and 
 converting the preliminary pin pattern into a postliminary pin pattern in a region of the interconnection layout of the standard cell layout, based on hitting information obtained upon the completion of the routing step, the postliminary pin pattern representative of a lower level metal interconnection of the lower metal layer of the semiconductor device, 
 wherein the postliminary pin pattern is different from the preliminary pin pattern. 
 
     
     
       2. The method of  claim 1 , wherein the postliminary pin pattern is different from the preliminary pin pattern in terms of size and arrangement. 
     
     
       3. The method of  claim 1 , wherein the converting of the preliminary pin pattern into the postliminary pin pattern places the postliminary pin pattern in a region that was occupied by the preliminary pin pattern such that the postliminary pin pattern and the preliminary pin pattern occupy overlapping regions in the method of producing the layout. 
     
     
       4. The method of  claim 1 , wherein the providing of the standard cell layout comprises:
 providing a logic layout including logic transistors; and 
 laying out a lower via pattern to connect the logic layout to the preliminary pin pattern. 
 
     
     
       5. The method of  claim 1 , wherein the laying out of the preliminary pin pattern comprises laying out ghost patterns, in which pin information for the routing step is contained, and
 the converting of the preliminary pin pattern into the postliminary pin pattern comprises converting one of the ghost patterns that hits the high-level interconnection layout into the postliminary pin pattern. 
 
     
     
       6. The method of  claim 1 , wherein the converting of the preliminary pin pattern into the postliminary pin pattern comprises preserving a first region of the preliminary pin pattern while removing a second region of the preliminary pin pattern, and
 the first region comprises a first hitting region to be connected to the high-level interconnection layout. 
 
     
     
       7. The method of  claim 1 , further comprising providing a plurality of cell layouts, each based on the standard cell layout,
 wherein the cell layouts have different interconnection layouts from one another, and 
 the converting of the preliminary pin pattern into the postliminary pin pattern comprises replacing the standard cell layout with one of the cell layouts, based on the hitting information. 
 
     
     
       8. The method of  claim 1 , further comprises laying out multiple ones of the standard cell layout, before the routing step. 
     
     
       9. A method of fabricating a semiconductor device, comprising:
 a process of generating a layout of a semiconductor device, the layout comprising a standard cell layout; 
 manufacturing a photomask having a mask pattern based on the layout of the semiconductor device; and 
 forming layers of metal lines and vias on a substrate using the photomask, the vias vertically connecting different layers of the metal lines, 
 wherein the generating of the layout of the semiconductor device comprises: 
 laying out a lower via pattern on a logic layout of the standard cell layout; 
 laying out a preliminary pin pattern on the lower via pattern; 
 performing a routing step on the standard cell layout, which places a high-level interconnection layout and an upper via pattern on the preliminary pin pattern, the upper via pattern connecting the preliminary pin pattern to an element of the high-level interconnection layout; and 
 generating a postliminary pin pattern connecting the lower via pattern to the upper via pattern, wherein the postliminary pin pattern and the preliminary pin pattern occupy overlapping regions in the process. 
 
     
     
       10. The method of  claim 9 , wherein the postliminary pin pattern is different from the preliminary pin pattern in terms of size and arrangement. 
     
     
       11. The method of  claim 9 , wherein the laying out of the preliminary pin pattern comprises laying out a ghost pattern, in which pin information for the routing step is contained, and wherein the upper via pattern is placed on the ghost pattern in the routing step, and
 the generating of the postliminary pin pattern comprises converting the ghost pattern into the pin pattern. 
 
     
     
       12. The method of  claim 9 , wherein the generating of the postliminary pin pattern comprises preserving a first region of the preliminary pin pattern while removing a second region of the preliminary pin pattern, and
 the first region comprises a region overlapped by the upper via pattern. 
 
     
     
       13. The method of  claim 12 , wherein the first region further comprises a region overlapping the lower via pattern. 
     
     
       14. The method of  claim 9 , wherein the process of generating of the layout of the semiconductor device further comprises generating a plurality of cell layouts each based on the standard cell layout, and wherein each one of the cell layouts comprises pin patterns that are different from those of each other of the cell layouts in terms of the sizes and arrangement of the pin patterns, and
 the generating of the postliminary pin pattern comprises replacing the standard cell layout with one of the cell layouts in consideration of the location of the upper via pattern. 
 
     
     
       15. A method of fabricating a semiconductor device, comprising:
 a process of generating a layout of a semiconductor device, the layout comprising a standard cell layout; 
 manufacturing a photomask having a mask pattern based on the layout of the semiconductor device; and 
 forming layers of metal lines and vias on a substrate using the photomask, the vias vertically connecting different layers of the metal lines, 
 wherein the generating of the layout of the semiconductor device comprises: 
 laying out a lower via pattern on a logic layout of the standard cell layout; 
 laying out a preliminary pin pattern on the lower via pattern; 
 performing a routing step on the standard cell layout, which places a high-level interconnection layout and an upper via pattern on the preliminary pin pattern, the upper via pattern connecting the preliminary pin pattern to an element of the high-level interconnection layout; and 
 changing size of the preliminary pin pattern to generate a postliminary pin pattern connecting the lower via pattern to the upper via pattern. 
 
     
     
       16. The method of  claim 15 , wherein the laying out of the preliminary pin pattern comprises laying out a ghost pattern, in which pin information for the routing step is contained, and wherein the upper via pattern is placed on the ghost pattern in the routing step, and
 the generating of the postliminary pin pattern comprises converting the ghost pattern into the pin pattern. 
 
     
     
       17. The method of  claim 15 , wherein the generating of the postliminary pin pattern comprises preserving a first region of the preliminary pin pattern while removing a second region of the preliminary pin pattern, and
 the first region comprises a region overlapped by the upper via pattern. 
 
     
     
       18. The method of  claim 17 , wherein the first region further comprises a region overlapping the lower via pattern. 
     
     
       19. The method of  claim 15 , wherein the process of generating of the layout of the semiconductor device further comprises generating a plurality of cell layouts each based on the standard cell layout, and wherein each one of the cell layouts comprises pin patterns that are different from those of each other of the cell layouts in terms of the sizes and arrangement of the pin patterns, and
 the generating of the postliminary pin pattern comprises replacing the standard cell layout with one of the cell layouts in consideration of the location of the upper via pattern. 
 
     
     
       20. An integrated circuit comprising:
 a substrate;   a first active region;   a second active region which is spaced apart from the first active region in a first direction;   a first power line which is extending parallel to a second direction;   a second power line which is extending parallel to the second direction;   a plurality of gate patterns which are extending parallel to the first direction, wherein the plurality of gate patterns are spaced apart from each other in the second direction;   a first contact which is provided within at least one of the first active region and the second active region, and disposed on at least one of the plurality of gate patterns;   a lower metal line;   an upper metal line;   a via connecting the lower metal line to the upper metal line;   a plurality of fins extending in the second direction crossing the first direction, wherein the plurality of fins are formed on the at least one of the first active region and the second active region;   a source/drain region which is provided in portions of the at least one of the first active region and the second active region, and positioned at both sides of the at least one of the plurality of gate patterns; and   a second contact which is connected to the source/drain region;   wherein the plurality of gate patterns are provided on the plurality of fins as extending across the plurality of fins in the first direction and parallel to each other;   wherein the first contact is disposed in a first layer, the lower metal line is disposed in a second layer, and the upper metal line is disposed in a third layer;   wherein the first contact electrically connects the at least one of the plurality of gate patterns to the lower metal line;   wherein the first contact includes a first portion contacting the at least one of the plurality of gate patterns and a second portion contacting the lower metal line;   wherein the first active region and the second active region comprise a PMOSFET region and an NMOSFET region;   wherein a height of the first contact is greater than a height of the via.    
     
     
       21. The integrated circuit of claim 20, wherein the first to third layers are an interlayer insulating layer.  
     
     
       22. The integrated circuit of claim 20, wherein the source/drain region is epitaxial pattern.  
     
     
       23. The integrated circuit of claim 20, wherein the source/drain region is formed of or comprise a semiconductor material having a lattice constant different from the substrate.  
     
     
       24. The integrated circuit of claim 20, wherein the second contact includes a plurality of second contacts that are arranged along the plurality of fins and in the second direction.  
     
     
       25. The integrated circuit of claim 20 further comprising a capping pattern which is provided to cover a top surface of each of the plurality of gate patterns.  
     
     
       26. The integrated circuit of claim 20 further comprising a plurality of first isolation layers which are provided at both sides of each of the plurality of fins.  
     
     
       27. The integrated circuit of claim 26 further comprising a second isolation layer which is interposed between the first active region and the second active region.  
     
     
       28. The integrated circuit of claim 27, wherein a step-shaped recess is formed on a base of the second isolation layer.  
     
     
       29. The integrated circuit of claim 27, wherein the second isolation layer defines PMOSFET and NMOSFET regions.  
     
     
       30. The integrated circuit of claim 27, wherein a depth of the second isolation layer is greater than a depth of the plurality of first isolation layers.  
     
     
       31. The integrated circuit of claim 20, wherein the lower metal line extends parallel to the second direction.  
     
     
       32. The integrated circuit of claim 20, wherein the upper metal line extends parallel to the first direction.  
     
     
       33. An integrated circuit comprising:
 a substrate;   a first active region;   a second active region which is spaced apart from the first active region in a first direction;   a first power line which is extending parallel to a second direction;   a second power line which is extending parallel to the second direction;   a first gate pattern which is extending parallel to the first direction across at least one of the first active region and the second active region;   a second gate pattern which is extending parallel to the first direction across the at least one of the first active region and the second active region, wherein the second gate pattern is spaced apart from the first gate pattern in the second direction;   a third gate pattern which is extending parallel to the first direction across the at least one of the first active region and the second active region, wherein the third gate pattern is spaced apart from the second gate pattern in the second direction;   a gate insulating pattern comprising a dielectric layer;   a first contact which is provided within the at least one of the first active region and the second active region and disposed on at least one of the first to third of gate patterns;   a first metal line extending parallel to the second direction;   a second metal line extending parallel to the first direction;   a third metal line extending parallel to the second direction;   a via connecting the second metal line to the third metal line;   a first fin extending in the second direction crossing the first direction, wherein the first fin is formed on the first active region;   a second fin extending in the second direction crossing the first direction, wherein the second fin is formed on the first active region;   a third fin extending in the second direction crossing the first direction, wherein the third fin is formed on the second active region;   a fourth fin extending in the second direction crossing the first direction, wherein the fourth fin is formed on the second active region;   a source/drain region which is provided on portions of the at least one of the first active region and the second active region and positioned at both sides of the at least one of the first to third of gate patterns; and   a second contact which is connected to the source/drain region;   wherein the first contact electrically connects the at least one of the first to third gate patterns to the first metal line;   wherein the first contact includes a first portion contacting the at least one of the first to third of gate patterns and a second portion contacting the first metal line;   wherein the first to third gate patterns are provided on the first to fourth fins as extending across the first to fourth fins in the first direction and parallel to each other;   wherein a height of the first contact is greater than a height of the via.    
     
     
       34. The integrated circuit of claim 33, wherein the first metal line, the second metal line, and the third metal line are disposed in an interlayer insulating layer.  
     
     
       35. The integrated circuit of claim 33, wherein the source/drain region is epitaxial pattern.  
     
     
       36. The integrated circuit of claim 33, wherein the source/drain region is formed of or comprises a semiconductor material having a lattice constant different from the substrate.  
     
     
       37. The integrated circuits of claim 33, wherein the second contact includes a plurality of second contacts that are arranged along the first to fourth fins and in the second direction.  
     
     
       38. The integrated circuit of claim 33 further comprising a capping pattern which is provided to cover a top surface of each of the first to third gate patterns.  
     
     
       39. The integrated circuit of claim 33 further comprising a plurality of first isolation layers which are provided at both sides of each of the first to fourth fins as extending in the second direction.  
     
     
       40. The integrated circuit of claim 39 further comprising a second isolation layer which is interposed between the first active region and the second active region.  
     
     
       41. The integrated circuit of claim 40, wherein a step-shaped recess is formed on a base of the second isolation layer.  
     
     
       42. The integrated circuit of claim 33, wherein the first active region and the second active region comprise a PMOSFET region and an NMOSFET region.  
     
     
       43. The integrated circuit of claim 40, wherein a depth of the second isolation layer is greater than a depth of the plurality of first isolation layers.  
     
     
       44. The integrated circuit of claim 33, wherein the first metal line comprises five pin regions.  
     
     
       45. The integrated circuit of claim 33, wherein at least one of the second metal line and the third metal line comprises five pin regions.  
     
     
       46. A set of integrated circuits comprising:
 a first standard cell comprising:
 a first active region; 
 a second active region which is spaced apart from the first active region in a first direction; 
 a first gate pattern which is extending parallel to the first direction across at least one of the first active region and the second active region; 
 a second gate pattern which is extending parallel to the first direction across the at least one of the first active region and the second active region, wherein the second gate pattern is spaced apart from the first gate pattern in a second direction; 
 a third gate pattern which is extending parallel to the first direction across the at least one of the first active region and the second active region, wherein the third gate pattern is spaced apart from the second gate pattern in the second direction; 
 a first contact which is provided within the at least one of the first active region and the second active region and disposed on the second gate pattern; 
 a first lower metal line; and 
 a first upper metal line; 
 a second standard cell comprising: 
 a third active region; 
 a fourth active region which is spaced apart from the second active region in the first direction; 
 a fourth gate pattern which is extending parallel to the first direction across at least one of the third active region and the fourth active region; 
 a fifth gate pattern which is extending parallel to the first direction across the at least one of the third active region and the fourth active region, 
 wherein the fifth gate pattern is spaced apart from the fourth gate pattern in the second direction; 
 a sixth gate pattern which is extending parallel to the first direction across the at least one of the third active region and the fourth active region, wherein the sixth gate pattern is spaced apart from the fifth gate pattern in the second direction; 
 a second contact which is provided within the at least one of the third active region and the fourth active region and disposed on the sixth gate pattern; 
 a second lower metal line; and 
 a second upper metal line; 
 a plurality of fins extending in the second direction crossing the first direction, wherein the plurality of fins are formed on at least one of first to fourth active regions; 
 a first power line which is extending parallel to the second direction; and 
 a second power line which is extending parallel to the second direction; 
 wherein the first contact and the second contact are disposed in a first layer, the first lower metal line and the second lower metal line are disposed in a second layer, and the first upper metal line and the second upper metal line are disposed in a third layer; 
 wherein the first contact electrically connects the second gate pattern to the first lower metal line; 
 wherein the second contact electrically connects the sixth gate pattern to the second lower metal line; 
 wherein the first standard cell and the second standard cell are adjacent to each other in the second direction.  
   
     
     
       47. The set of integrated circuits of claim 46, wherein the first to third layers are an interlayer insulating layer.  
     
     
       48. The set of integrated circuits of claim 46 further comprising a source/drain region which is provided in portions of the at least one of the first to fourth active regions, and positioned at both sides of the at least one of the first to sixth gate patterns.  
     
     
       49. The set of integrated circuits of claim 48 further comprising a third contact which is connected to the source/drain region.  
     
     
       50. The set of integrated circuits of claim 48, wherein the source/drain region is epitaxial pattern.  
     
     
       51. The set of integrated circuits of claim 48, wherein the source/drain region is formed of or comprise a semiconductor material having a lattice constant different from a substrate.  
     
     
       52. The set of integrated circuits of claim 49, wherein the third contact includes a plurality of third contacts that are arranged along the plurality of fins and in the second direction.  
     
     
       53. The set of integrated circuits of claim 46 further comprising a capping pattern which is provided to cover a top surface of each of the first to sixth gate patterns.  
     
     
       54. The set of integrated circuits of claim 46 further comprising a plurality of first isolation layers which are provided at both sides of each of the plurality of fins.  
     
     
       55. The set of integrated circuits of claim 54 further comprising a second isolation layer which is interposed between the first active region and the second active region.  
     
     
       56. The set of integrated circuits of claim 55, wherein a step-shaped recess is formed on a base of the second isolation layer.  
     
     
       57. The set of integrated circuits of claim 46, wherein the first to fourth active regions comprise a PMOSFET region and an NMOSFET region.  
     
     
       58. The set of integrated circuits of claim 55, wherein a depth of the second isolation layer is greater than a depth of the plurality of first isolation layers.  
     
     
       59. The set of integrated circuits of claim 46, wherein a boundary between the first standard cell and the second standard cell is located between the third gate pattern and the fourth gate pattern.  
     
     
       60. A set of integrated circuits comprising:
 a first standard cell comprising:   a first active region;   a second active region which is spaced apart from the first active region in a first direction;   a first gate pattern which is extending parallel to the first direction across at least one of the first active region and the second active region;   a second gate pattern which is extending parallel to the first direction across the at least one of the first active region and the second active region, wherein the second gate pattern is spaced apart from the first gate pattern in a second direction;   a third gate pattern which is extending parallel to the first direction across the at least one of the first active region and the second active region, wherein the third gate pattern is spaced apart from the second gate pattern in the second direction;   a first contact which is provided within the at least one of the first active region and the second active region and disposed on the second gate pattern;   a first lower metal line; and   a first upper metal line;   a second standard cell comprising:   a third active region;   a fourth active region which is spaced apart from the second active region in the first direction;   a fourth gate pattern which is extending parallel to the first direction across at least one of the third active region and the fourth active region;   a second contact which is provided within the at least one of the third active region and the fourth active region and disposed on the fourth gate pattern;   a second lower metal line; and   a second upper metal line;   a plurality of fins extending in a second direction crossing the first direction, wherein the plurality of fins are formed on at least one of first to fourth active regions;   a first power line which is extending parallel to the second direction; and   a second power line which is extending parallel to the second direction;   wherein the first contact electrically connects the second gate pattern to the first lower metal line;   wherein the second contact electrically connects the fourth gate pattern to the second lower metal line;   wherein the first standard cell and the second standard cell are adjacent to each other in the second direction;   wherein a boundary between the first standard cell and the second standard cell is located between the third gate pattern and the fourth gate pattern.    
     
     
       61. The set of integrated circuits of claim 60 further comprising a plurality of first isolation layers which are provided at both sides of each of the plurality of fins.  
     
     
       62. The set of integrated circuits of claim 61 further comprising a second isolation layer which is interposed between the first active region and the second active region.  
     
     
       63. The set of integrated circuits of claim 61, wherein a step-shaped recess is formed on a base of the second isolation layer.  
     
     
       64. The set of integrated circuits of claim 61, wherein the second isolation layer defines PMOSFET and NMOSFET regions.  
     
     
       65. The set of integrated circuits of claim 61, wherein a depth of the second isolation layer is greater than a depth of the plurality of first isolation layers.