Shift register and driving method thereof gate driving circuit and display apparatus

Abstract

A shift register includes: an input unit, configured to provide an input signal to a first node; a pull-up unit, configured to provide a voltage of a first supply voltage terminal to an output terminal; a pull-up control unit, configured to provide the voltage of the first supply voltage terminal or a voltage of a second supply voltage terminal to a second node; a pull-down unit, configured to provide a third clock signal from a third clock signal terminal to the output terminal; a pull-down control unit, configured to provide the voltage of the first supply voltage terminal to the first node; a first noise reduction unit, configured to reduce electrical leakage of the input unit to the first node; and a second noise reduction unit, configured to reduce electrical leakage of the pull-down control unit to the first node.

What is claimed is: 
     
       1. A shift register, comprising:
 an input unit, a first terminal of the input unit being connected with being electrically connected with an input terminal of the shift register to receive an input signal from the input terminal, a second terminal of the input unit being connected with being electrically connected with a first clock signal terminal, and a third terminal of the input unit being connected with being electrically connected with a first node, and the input unit being configured to provide the input signal to the first node under control of a first clock signal from the first clock signal terminal; 
 a pull-up unit, a first terminal of the pull-up unit being connected with being electrically connected with a first supply voltage terminal, a second terminal of the pull-up unit being connected with being electrically connected with a second node, and a third terminal of the pull-up unit being connected with being electrically connected with an output terminal of the shift register, and the pull-up unit being configured to provide a voltage of the first supply voltage terminal to the output terminalunder control of a voltage of the second node; 
 a pull-up control unit, a first terminal of the pull-up control unit being connected with a second clock signal terminal, a second terminal of the pull-up control unit being connected with the first supply voltage terminal, a third terminal of the pull-up control unit being connected with the second node, a fourth terminal of the pull-up control unit being connected with the input terminal, and a fifth terminal of the pull-up control unit being connected with a second supply voltage terminal, and the pull-up control unit being configured to provide the voltage of the first supply voltage terminal to the second node under control of the input signal or to provide a voltage of the second supply voltage terminal to the second node under control of a second clock signal from the second clock signal terminal; 
 a pull-down unit, a first terminal of the pull-down unit being connected with the first node, a second terminal of the pull-down unit being connected with a third clock signal terminal, and a third terminal of the pull-down unit being connected with the output terminal, and the pull-down unit being configured to provide a third clock signal from the third clock signal terminal to the output terminal under control of a voltage of the first node; 
 a pull-down control unit, a first terminal of the pull-down control unit being connected with being electrically connected with the first supply voltage terminal, a second terminal of the pull-down control unit being connected with being electrically connected with the first node, and a third terminal of the pull-down control unit being connected with being electrically connected with the second node, and the pull-down control unit being configured to provide the voltage of the first supply voltage terminal to the first node under control of a voltage of the second node; 
 a first noise reduction unit, a first terminal of the first noise reduction unit being connected with the third clock signal terminal, a second terminal of the first noise reduction unit being connected with the output terminal, and a third terminal of the first noise reduction unit being connected with the third node, and the first noise reduction unit being configured to reduce electrical leakage of the input unit to the first node by adjusting a voltage of the third node; and 
 a second noise reduction unit, a first terminal of the second noise reduction unit being connected with being electrically connected with a fourth node, a second terminal of the second noise reduction unit being connected with being electrically connected with the first node, and a third terminal of the second noise reduction unit being connected with the second supply voltage terminal, and the second noise reduction unit being configured to reduce electrical leakage of the pull-down control unit to the first node by adjusting a voltage of the fourth node; 
 wherein the third node is a connection node between the first noise reduction unit and the input unit, and the fourth node is a connection node between the second noise reduction unit and the pull-down control unit. 
 
     
     
       2. The shift register of  claim 1 , wherein the input unit comprises:
 a first transistor, with a gate electrode of the first transistor being connected with the first clock signal terminal, a first electrode of the first transistor being connected with the input terminal and a second electrode of the first transistor being connected with the third node; and   a second transistor, with a gate electrode of the second transistor being connected with the first clock signal terminal, a first electrode of the second transistor being connected with the third node and a second electrode of the second transistor being connected with the first node.   
     
     
       3. The shift register of  claim 2 , wherein the pull-up unit comprises:
 a third transistor, with a gate electrode of the third transistor being connected with the second node, a first electrode of the third transistor being connected with the first supply voltage terminal and a second electrode of the third transistor being connected with the output terminal; and   a first capacitor, with a first end of the first capacitor being connected with the second node and a second end of the first capacitor being connected with the first supply voltage terminal.   
     
     
       4. The shift register of  claim 3 , wherein the pull-up control unit comprises:
 a fourth transistor, with a gate electrode of the fourth transistor being connected with the input terminal, a first electrode of the fourth transistor being connected with the first supply voltage terminal and a second electrode of the fourth transistor being connected with the second node; and   a fifth transistor, with a gate electrode of the fifth transistor being connected with the second clock signal terminal, a first electrode of the fifth transistor being connected with the second node and a second electrode of the fifth transistor being connected with the second supply voltage terminal.   
     
     
       5. The shift register of  claim 4 , wherein the pull-down unit comprises:
 a sixth transistor, with a gate electrode of the sixth transistor being connected with the first node, a first electrode of the sixth transistor being connected with the output terminal and a second electrode of the sixth transistor being connected with the third clock signal terminal; and   a second capacitor, with a first end of the second capacitor being connected with the first node and a second end of the second capacitor being connected with the output terminal.   
     
     
       6. The shift register of  claim 5 , wherein the pull-down control unit comprises:
 a seventh transistor, with a gate electrode of the seventh transistor being connected with the second node, a first electrode of the seventh transistor being connected with the first supply voltage terminal and a second electrode of the seventh transistor being connected with the fourth node; and   an eighth transistor, with a gate electrode of the eighth transistor being connected with the second node, a first electrode of the eighth transistor being connected with the fourth node and a second electrode of the eighth transistor being connected with the first node.   
     
     
       7. The shift register of  claim 6 , wherein the first noise reduction unit comprises:
 a ninth transistor, with a gate electrode of the ninth transistor being connected with the output terminal, a first electrode of the ninth transistor being connected with the third clock signal terminal and a second electrode of the ninth transistor being connected with the third node.   
     
     
       8. The shift register of  claim 7 , wherein the second noise reduction unit comprises:
 a tenth transistor, with a gate electrode of the tenth transistor being connected with the first node, a first electrode of the tenth transistor being connected with the fourth node and a second electrode of the tenth transistor being connected with the second supply voltage terminal.   
     
     
       9. The shift register of  claim 8 , wherein the transistors are all p-type transistors. 
     
     
       10. The shift register of  claim 1 , wherein duty cycles of the first, second and third clock signal from the first, second and third clock signal terminal are 33%. 
     
     
       11. The shift register of  claim 1 , wherein the first supply voltage terminal is a high supply voltage terminal while the second supply voltage terminal is a low supply voltage terminal. 
     
     
       12. A driving method applicable to a shift register comprising an input unit, a pull-up unit, a pull-up control unit, a pull-down unit, a pull-down control unit, a first noise reduction unit and a second noise reduction unit, the driving method comprising:
 providing an input signal to a first node by the input unit;   providing a voltage of a first supply voltage terminal to an output terminal of the shift register by the pull-up unit;   providing the voltage of the first supply voltage terminal or a voltage of a second supply voltage terminal to a second node by the pull-up control unit;   providing a third clock signal from a third clock signal terminal to the output terminal by the pull-down unit;   providing the voltage of the first supply voltage terminal to the first node by the pull-down control unit;   reducing electrical leakage of the input unit to the first node by adjusting a voltage of a third node by the first noise reduction unit; and   reducing electrical leakage of the pull-down control unit to the first node by adjusting a voltage of a fourth node by the second noise reduction unit;   wherein the first node is a connection node among the input unit, the pull-down unit, the pull-down control unit and the second noise reduction unit, the second node is a connection node among the pull-up unit, the pull-up control unit, and the pull-down control unit, the third node is a connection node between the first noise reduction unit and the input unit, and the fourth node is a connection node between the second noise reduction unit and the pull-down control unit, the first supply voltage terminal is a high supply voltage terminal while the second supply voltage terminal is a low supply voltage terminal, and a duty cycle of the third clock signal from the third clock signal terminal is 33%.   
     
     
       13. A gate driving circuit, comprising the shift register according to  claim 1 . 
     
     
       14. A display apparatus, comprising the gate driving circuit according to  claim 13 . 
     
     
       15. The shift register of claim 1, further comprising:
 a pull-up control unit, a first terminal of the pull-up control unit being electrically connected with a second clock signal terminal, a second terminal of the pull-up control unit being electrically connected with the first supply voltage terminal, a third terminal of the pull-up control unit being electrically connected with the second node, a fourth terminal of the pull-up control unit being electrically connected with a second supply voltage terminal;   a pull-down unit, a first terminal of the pull-down unit being electrically connected with the first node, a second terminal of the pull-down unit being electrically connected with the output terminal, and the pull-down unit being configured to control a voltage of the output terminal under control of a voltage of the first node; and   a first noise reduction unit, being electrically connected with a third node;   wherein the third node is a connection node between the first noise reduction unit and the input unit.   
     
     
       16. The shift register of claim 15, wherein the input unit comprises:
 a first transistor, with a gate electrode of the first transistor being electrically connected with the first clock signal terminal, a first electrode of the first transistor being electrically connected with the input terminal and a second electrode of the first transistor being electrically connected with the third node; and   a second transistor, with a first electrode of the second transistor being electrically connected with the third node and a second electrode of the second transistor being electrically connected with the first node.   
     
     
       17. The shift register of claim 16, wherein the pull-up unit comprises:
 a third transistor, with a gate electrode of the third transistor being electrically connected with the second node, a first electrode of the third transistor being electrically connected with the first supply voltage terminal and a second electrode of the third transistor being electrically connected with the output terminal; and   a first capacitor, with a first end of the first capacitor being electrically connected with the second node and a second end of the first capacitor being electrically connected with the first supply voltage terminal.   
     
     
       18. The shift register of claim 17, wherein the pull-up control unit comprises:
 a fourth transistor, being electrically connected with the second node; and   a fifth transistor, with a gate electrode of the fifth transistor being electrically connected with the second clock signal terminal.   
     
     
       19. The shift register of claim 18, wherein the pull-down unit comprises:
 a sixth transistor, with a gate electrode of the sixth transistor being electrically connected with the first node, and a first electrode of the sixth transistor being electrically connected with the output terminal.   
     
     
       20. The shift register of claim 19, wherein the pull-down control unit comprises:
 a seventh transistor, with a gate electrode of the seventh transistor being electrically connected with the second node, a first electrode of the seventh transistor being electrically connected with the first supply voltage terminal and a second electrode of the seventh transistor being electrically connected with the fourth node.   
     
     
       21. The shift register of claim 20, wherein the first noise reduction unit comprises:
 a ninth transistor, being electrically connected with the third node.   
     
     
       22. The shift register of claim 21, wherein the second noise reduction unit comprises:
 a tenth transistor, with a gate electrode of the tenth transistor being electrically connected with the first node, and a first electrode of the tenth transistor being electrically connected with the fourth node.   
     
     
       23. The shift register of claim 16, wherein the pull-up unit comprises a third transistor and a first capacitor, the pull-up control unit comprises a fourth transistor and a fifth transistor, the pull-down unit comprises a sixth transistor, the pull-down control unit comprises a seventh transistor, the first noise reduction unit comprises a ninth transistor, the second noise reduction unit comprises a tenth transistor, and the first to tenth transistors are all p-type transistors. 
     
     
       24. The shift register of claim 15, wherein a duty cycle of the first from the first clock signal terminal is 33%. 
     
     
       25. A shift register, comprising a first control unit, an input unit, a second control unit, a third control unit, a fourth control unit, a fifth control unit, and a sixth control unit, wherein
 the input unit is electrically connected with an input terminal, a first node and a third node, the input unit comprises a first transistor and a second transistor, a first electrode of the first transistor is electrically connected with the input terminal, a first electrode of the second transistor is electrically connected with the third node, and a second electrode of the second transistor is electrically connected with the first node;   the first control unit is electrically connected with the third node;   the second control unit is electrically connected with a second node and a fourth node, the second control unit comprises a seventh transistor, a gate electrode of the seventh transistor is electrically connected with the second node, a first electrode of the seventh transistor is electrically connected with a first supply voltage terminal, and a second electrode of the seventh transistor is electrically connected with the fourth node;   the sixth control unit is electrically connected with the first node and the fourth node, the sixth control unit comprises a tenth transistor, a gate electrode of the tenth transistor is electrically connected with the first node, and a first electrode of the tenth transistor is electrically connected with the fourth node;   the third control unit is electrically connected with the second node;   the fourth control unit is electrically connected with second node and an output terminal, the fourth control unit comprises a third transistor and a first capacitor, a first electrode of the third transistor is electrically connected with the first supply voltage terminal, a gate electrode of the third transistor is electrically connected with a first electrode of the first capacitor, a second electrode of the third transistor is electrically connected with the output terminal, and a second electrode of the first capacitor is electrically connected with the first supply voltage terminal; and   the fifth control unit is electrically connected with the first node and the output terminal, the fifth control unit comprises a sixth transistor, a gate electrode of the sixth transistor is electrically connected with the first node, and a first electrode of the sixth transistor is electrically connected with the output terminal.   
     
     
       26. A shift register, comprising a first noise reduction unit, an input unit, a pull-down control unit, a pull-up control unit, a pull-up unit, a pull-down unit, and a second noise reduction unit, wherein
 the input unit is electrically connected with an input terminal, a first node and a third node, the input unit comprises a first transistor and a second transistor, a first electrode of the first transistor is electrically connected with the input terminal, a first electrode of the second transistor is electrically connected with the third node, and a second electrode of the second transistor is electrically connected with the first node;   the first noise reduction unit is electrically connected with the third node;   the pull-down control unit is electrically connected with a second node and a fourth node, the pull-down control unit comprises a seventh transistor, a gate electrode of the seventh transistor is electrically connected with the second node, a first electrode of the seventh transistor is electrically connected with a first supply voltage terminal, and a second electrode of the seventh transistor is electrically connected with the fourth node;   the second noise reduction unit is electrically connected with the first node and the fourth node, the second noise reduction unit comprises a tenth transistor, a gate electrode of the tenth transistor is electrically connected with the first node, and a first electrode of the tenth transistor is electrically connected with the fourth node;   the pull-up control unit is electrically connected with the second node;   the pull-up unit is electrically connected with second node and an output terminal, the pull-up unit comprises a third transistor and a first capacitor, a first electrode of the third transistor is electrically connected with the first supply voltage terminal, a gate electrode of the third transistor is electrically connected with a first electrode of the first capacitor, a second electrode of the third transistor is electrically connected with the output terminal, and a second electrode of the first capacitor is electrically connected with the first supply voltage terminal; and   the pull-down unit is electrically connected with the first node and the output terminal, the pull-down unit comprises a sixth transistor, a gate electrode of the sixth transistor is electrically connected with the first node, and a first electrode of the sixth transistor is electrically connected with the output terminal.