Nonvolatile semiconductor memory device and memory system having termination circuit with variable resistor

Abstract

A memory device includes a nonvolatile semiconductor memory cell array, a plurality of terminals through which control signals are received to control the memory device, an on-die termination circuit connected to at least one of the terminals and having a variable resistor, and a control circuit. The control circuit is configured to enable the on-die termination circuit in response to an enabling signal to enable the on-die termination circuit, with a resistance of the variable registor resistor at different values depending on whether a control signal is asserted or deasserted when the enabling signal is received.

What is claimed is: 
     
       1. A memory device, comprising:
 a nonvolatile semiconductor memory cell array; 
 a plurality of terminals through which control signals are received to control for the memory device, the plurality of terminals including a first terminal to receive data, a second terminal to receive a clock signal, and a third terminal to receive a read enable signal, and a fourth terminal to receive a first signal; 
 an on-die termination circuit connected to at least one or more of the first, second, and third, and fourth terminals and having a variable resistor; and 
 a control circuit configured to enable the on-die termination circuit in response to an enabling the first signal to enable the on-die termination circuit, a resistance of the variable resistor of the on-die termination circuit being set at different values depending on whether a control second signal is asserted or deasserted when the enabling first signal is received. 
 
     
     
       2. The memory device according to  claim 1 , wherein
 the control second signal is the read enable signal, which enables a read operation in the memory device. 
 
     
     
       3. The memory device according to  claim 1 , further comprising:
 a memory unit that stores setting information of whether or not the on-die termination circuit is operable, wherein 
 when the setting information indicates that the on-die termination circuit is set to be inoperable, the control circuit does not enable the on-die termination circuit even when the enabling first signal is received. 
 
     
     
       4. The memory device according to  claim 1 , wherein
 the plurality of terminals, the on-die termination circuit, and the control circuit are included in a chip disposed on a substrate, and 
 the nonvolatile semiconductor memory cell array is included in one of a plurality of semiconductor memory chips stacked on the substrate. 
 
     
     
       5. The memory device according to  claim 1 , wherein
 the nonvolatile semiconductor memory cell array, the plurality of terminals, the on-die termination circuit, and the control circuit are included in one of a plurality of semiconductor memory chips stacked on a substrate. 
 
     
     
       6. The memory device according to  claim 1 , wherein
 the control circuit enables the on-die termination circuit, only when a chip enable signal for the memory device that is received at one of the plurality of terminals is deasserted. 
 
     
     
       7. The memory device according to  claim 1 , further comprising:
 a memory unit that stores storing setting information of indicating the operability of the on-die termination circuit when if the control second signal is asserted, and 
 the controller control circuit does not enable the on-die termination circuit if the setting information indicates as the on-die termination circuit is inoperable, even when the enabling signal is received while the control signal is asserted. 
 
     
     
       8. The memory device according to  claim 1 , further comprising:
 a memory unit that stores storing setting information of indicating the operability of the on-die termination circuit when if the control second signal is deasserted, and 
 the controller control circuit does not enable the on-die termination circuit if the setting information indicates as the on-die termination circuit is inoperable, even when the enabling signal is received while the control signal is deasserted. 
 
     
     
       9. The memory device according to  claim 1 , wherein
 the on-die termination circuit includes a first switching element, the variable resistor, and a second switching element that are connected in series between a power source terminal and a ground terminal, and 
 the on-die termination circuit is enabled by switching on the first and second switching elements. 
 
     
     
       10. A memory system, comprising:
 a plurality of nonvolatile semiconductor memory modules, each including:
 a plurality of terminals through which control signals are received to control for the nonvolatile semiconductor memory module, 
 an on-die termination circuit connected to at least one of the terminals, and 
 a control circuit configured to control the on-die termination circuit; and 
 
 a controller configured to;: 
 enable a first nonvolatile semiconductor memory module, and 
 while the first nonvolatile semiconductor memory module is enabled, deassert a first signal for enabling a second nonvolatile semiconductor memory module to disable the second nonvolatile semiconductor memory module, and transmit an enabling signal to enable the on-die termination circuit of the second nonvolatile semiconductor memory module. 
 
 
     
     
       11. The memory system according to  claim 10 , wherein
 the controller transmits the enabling signal to the second nonvolatile semiconductor memory module after transmitting a command to the first nonvolatile semiconductor memory module. 
 
     
     
       12. The memory system according to  claim 10 , wherein
 the controller deasserts the enabling signal to the second nonvolatile semiconductor memory module upon a disabling of the first semiconductor memory module. 
 
     
     
       13. The memory system according to  claim 10 , wherein
 when the controller transmits data to be written into the first nonvolatile semiconductor memory module that is enabled, the controller transmits the enabling signal before transmitting the data to the first nonvolatile semiconductor memory module. 
 
     
     
       14. The memory system according to  claim 10 , wherein
 when the controller operates to read data from the first nonvolatile semiconductor memory module that is enabled, the controller transmits the enabling signal before the data are read reading data from the first nonvolatile semiconductor memory module. 
 
     
     
       15. The memory system according to  claim 10 , wherein
 the controller transmits a signal to a terminal of the second nonvolatile semiconductor memory module, as a write protection signal to prohibit data writing into the second nonvolatile semiconductor memory module for a predetermined period of time after the second nonvolatile semiconductor memory module has been powered on, and as the enabling signal after the predetermined period of time. 
 
     
     
       16. The memory system according to  claim 15 , wherein deassertion of the enabling signal causes the second nonvolatile semiconductor memory module to prohibit data writing therein. 
     
     
       17. The memory system according to  claim 10 , wherein
 when data are read from the first nonvolatile semiconductor memory module that is enabled, the controller transmits the enabling signal while a read enable signal to enable data reading is asserted, and 
 when data are written into the first nonvolatile semiconductor memory module that is enabled, the controller transmits the enabling signal while the read enable signal is deasserted. 
 
     
     
       18. A memory device, comprising:
 a nonvolatile semiconductor memory cell array;   a first terminal for data;   a second terminal for a clock signal;   a third terminal for a read enable signal;   an on-die termination circuit connected to one or more of the first, second, and third terminals, the on-die termination circuit including:
 a first switching element, 
 a first variable resistor connected in series with the first switching element between a first power source terminal and the at least one of the first, second, and third terminals, 
 a second variable resistor, and 
 a second switching element connected in series with the first switching element between a second power source terminal and at least one of the first, second, and third terminals; and 
   a control circuit configured to enable the on-die termination circuit in response to an enabling signal supplied to the control circuit.    
     
     
       19. The memory device according to claim 18, wherein an operating mode of the on-die termination circuit is set according to whether a read enable signal for enabling a read operation is being asserted while the enabling signal supplied to the control circuit is asserted.  
     
     
       20. The memory device according to claim 18, further comprising:
 a memory unit that stores setting information indicating whether the on-die termination circuit is operable, wherein   when the setting information indicates that the on-die termination circuit is set to be inoperable, the control circuit does not enable the on-die termination circuit even when the enabling signal is received.    
     
     
       21. The memory device according to claim 18, wherein the control circuit enables the on-die termination circuit only if a chip enable signal is also deasserted.  
     
     
       22. The memory device according to claim 18, further comprising:
 a memory unit that stores setting information, and   the control circuit is configured to not enable the on-die termination circuit if the setting information indicates the on-die termination circuit is inoperable.    
     
     
       23. The memory device according to claim 18, wherein the second power source terminal is a ground terminal.  
     
     
       24. The memory device according to claim 18, wherein resistances of the first variable resistor and the second variable resistor are set at a first value when the enabling signal is received while a control signal is being asserted and set at a second value, different from the first value, when the enabling signal is received while the control signal is being deasserted.