Method of manufacturing semiconductor device, and semiconductor device

Abstract

A method of manufacturing a semiconductor device includes: the first step of forming a gate electrode over a silicon substrate, with a gate insulating film; and the second step of digging down a surface layer of the silicon substrate by etching conducted with the gate electrode as a mask. The method of manufacturing the semiconductor device further includes the third step of epitaxially growing, on the surface of the dug-down portion of the silicon substrate, a mixed crystal layer including silicon and atoms different in lattice constant from silicon so that the mixed crystal layer contains an impurity with such a concentration gradient that the impurity concentration increases along the direction from the silicon substrate side toward the surface of the mixed crystal layer.

What is claimed is: 
     
       1. A method of manufacturing a semiconductor device, comprising:
 the first step of forming a gate electrode over a silicon substrate, with a gate insulating film;   the second step of digging down a surface layer of said silicon substrate by etching conducted with said gate electrode as a mask; and   the third step of epitaxially growing, on the surface of said dug-down portion of said silicon substrate, a mixed crystal layer including silicon and atoms different in lattice constant from silicon so that said mixed crystal layer contains an impurity with such a concentration gradient that the impurity concentration increases along the direction from said silicon substrate side toward the surface of said mixed crystal layer,   wherein,   said third step includes epitaxially growing said mixed crystal layer so that said mixed crystal layer contains the impurity with said concentration gradient such that said impurity concentration increases stepwise along the direction from said silicon substrate side toward the surface of said mixed crystal layer.   
     
     
       2. The method of manufacturing a semiconductor device as set forth in  claim 1 ,
 wherein said semiconductor device is a p-type field effect transistor, and   said third step includes epitaxially growing, on the surface of said silicon substrate, said mixed crystal layer including silicon and germanium so that said mixed crystal layer contains the p-type impurity with said concentration gradient.   
     
     
       3. The method of manufacturing a semiconductor device as set forth in  claim 1 ,
 wherein said semiconductor device is an n-type field effect transistor, and   said third step includes epitaxially growing, on the surface of said silicon substrate, said mixed crystal layer including silicon and carbon so that said mixed crystal layer contains the n-type impurity with said concentration gradient.   
     
     
       4. The method of manufacturing a semiconductor device as set forth in  claim 1 ,
 wherein said third step includes epitaxially growing said mixed crystal layer so that said mixed crystal layer contains the impurity with said concentration gradient such that said impurity concentration increases continuously along the direction from said silicon substrate side toward the surface of said mixed crystal layer.   
     
     
       5. The method of manufacturing a semiconductor device as set forth in  claim 1 ,
 wherein said mixed crystal layer includes a first layer, a second layer, and a third layer sequentially layered in a stacked state, and   said third step includes the steps of:
 forming said first layer on the surface of said dug-down portion of said silicon substrate so that said first layer contains said impurity in the lowest concentration among said three layers; 
 forming said second layer on said first layer so that said second layer contains said impurity with such a concentration gradient that the impurity concentration in said second layer increases from the impurity concentration in said first layer to the impurity concentration in said third layer; and 
 forming said third layer on said second layer so that said third layer contains said impurity in the highest concentration among said three layers. 
   
     
     
       6. A method of manufacturing a semiconductor device, comprising:
 a first step of forming a mask, wherein the mask comprises:
 a first gate electrode over a silicon substrate, 
 a first side wall on a lateral side of the first gate electrode, 
 a second gate electrode over the silicon substrate, and 
 a second side wall on a lateral side of the second gate electrode; 
   a second step of digging down by etching, with the mask, a surface of the silicon substrate in a manner that forms a dug-down portion of the silicon substrate; and   a third step of epitaxially growing a mixed crystal layer that includes:
 silicon and atoms different in lattice constant from silicon so that the mixed crystal layer contains an impurity with such a concentration gradient that a concentration of the impurity increases stepwise along a first direction from the silicon substrate toward a surface of the mixed crystal layer, 
   wherein the mixed crystal layer comprises:
 a first layer that is grown on a surface of the dug-down portion in a manner that causes the first layer to extend from the first side wall to the second side wall, and 
 a second layer that is grown on the first layer in a manner that causes the second layer to extend from the first side wall to the second side wall, 
 a third layer that is grown on the second layer, 
   wherein a concentration of the impurity in the first layer is lower than a concentration of the impurity in the second layer,   wherein the third layer is a topmost layer of the mixed crystal layer, protrudes in the first direction from a surface level of the silicon substrate, and has a film thickness of at least 50 nm.    
     
     
       7. The method of manufacturing a semiconductor device as set forth in claim 6, wherein the concentration of the impurity in the second layer is lower than a concentration of the impurity in the third layer.  
     
     
       8. The method of manufacturing a semiconductor device as set forth in claim 7, wherein the second layer is between the first layer and the third layer.  
     
     
       9. The method of manufacturing a semiconductor device as set forth in claim 7, wherein the third concentration is 1×10 19  to 5×10 20  cm −3 .  
     
     
       10. The method of manufacturing a semiconductor device as set forth in claim 7, wherein the first layer and the second layer and the third layer are formed by a same film-forming gases with a same flow rate.  
     
     
       11. The method of manufacturing a semiconductor device as set forth in claim 7, wherein the film thickness of the third layer is 50 to 100 nm.  
     
     
       12. The method of manufacturing a semiconductor device as set forth in claim 6, wherein the mask exposes the surface of the silicon substrate in the second step.  
     
     
       13. The method of manufacturing a semiconductor device as set forth in claim 6, wherein etching in the second step is isotropic etching.  
     
     
       14. The method of manufacturing a semiconductor device as set forth in claim 6, wherein the impurity is introduced in the third step using in-situ doping.  
     
     
       15. The method of manufacturing a semiconductor device as set forth in claim 6, wherein the second concentration varies continuously from the first concentration to the third concentration.  
     
     
       16. The method of manufacturing a semiconductor device as set forth in claim 6, wherein the first concentration is 1×10 18  to 1×10 19  cm −3 .  
     
     
       17. The method of manufacturing a semiconductor device as set forth claim 6, wherein the second concentration has a concentration gradient increasing from (1) a range of 1×10 18  to 1×10 19  cm −3  to (2) a range of 1×10 19  to 5×10 20  cm −3 .  
     
     
       18. The method of manufacturing a semiconductor device as set forth in claim 6, wherein the mixed crystal layer comprises an impurity selected from a group of consisting of boron, arsenic, phosphorus and a combination thereof.  
     
     
       19. The method of manufacturing a semiconductor device as set forth claim 6, wherein the semiconductor device is a p-type field effect transistor.  
     
     
       20. The method of manufacturing a semiconductor device as set forth in claim 6, wherein the impurity is a p-type impurity.  
     
     
       21. The method of manufacturing a semiconductor device as set forth in claim 20, wherein the atoms different in lattice constant from silicon is germanium.  
     
     
       22. The method of manufacturing a semiconductor device as set forth in claim 6, wherein the semiconductor device is an n-type field effect transistor.  
     
     
       23. The method of manufacturing a semiconductor device as set forth in claim 6, wherein the impurity is an n-type impurity.  
     
     
       24. The method of manufacturing a semiconductor device as set forth in claim 23, wherein the atoms different in lattice constant from silicon is carbon.  
     
     
       25. The method of manufacturing a semiconductor device as set forth in claim 6, wherein the film thickness of the first layer is 10 to 30 nm.  
     
     
       26. The method of manufacturing a semiconductor device as set forth in claim 6, wherein the film thickness of the second layer is 1 to 20 nm.  
     
     
       27. The method of manufacturing a semiconductor device as set forth in claim 6, wherein a depth of the dug-down portion is about 80 nm.