Systems and methods for minimizing static leakage of an integrated circuit

Abstract

A leakage manager system for adequately minimizing static leakage of an integrated circuit is disclosed. The leakage manager system includes a generator configured to generate a control signal to be applied to a sleep transistor. A monitor is configured to determine whether to adjust the control signal to adequately minimize the static leakage. In some embodiments, the monitor includes an emulated sleep transistor. A regulator is configured to adjust the control signal depending on the determination.

What is claimed is: 
     
       1. An integrated circuit comprising:
 a logic component, the logic component being either a logic gate or a storage cell, and the logic component including a sleep transistor in series with an electrical connection to a ground terminal;   a voltage generator configured to generate a negative voltage to be applied to the sleep transistor; and   controller circuitry configured to:   i) monitor drain-source current of the sleep transistor;   ii) make a determination of whether to adjust the negative voltage in connection with adequate minimization of a static leakage of the integrated circuit; and   iii) adjust the negative voltage depending on the determination.   
     
     
       2. The integrated circuit of  claim 1  wherein the controller circuitry is configured to continuously make determinations of whether to adjust the negative voltage in connection with the adequate minimization of the static leakage. 
     
     
       3. The integrated circuit of  claim 1  wherein the controller circuitry is configured to periodically make determinations of whether to adjust the negative voltage in connection with the adequate minimization of the static leakage. 
     
     
       4. The integrated circuit of  claim 1  wherein the voltage generator is configured to selectively generate the negative voltage. 
     
     
       5. The integrated circuit of  claim 1  wherein the voltage generator is a charge pump. 
     
     
       6. An integrated circuit comprising:
 a logic component, the logic component being either a logic gate or a storage cell, and the logic component including a sleep transistor in series with an electrical connection to a ground terminal;   a voltage generator configured to generate a negative voltage to be applied to the sleep transistor; and   controller circuitry configured to:   i) monitor a drain-source current and a drain-gate current of either the sleep transistor or an emulated sleep transistor;   ii) make a determination of whether to adjust the negative voltage in connection with adequate minimization of a static leakage of the integrated circuit; and   iii) adjust the negative voltage depending on the determination.   
     
     
       7. The integrated circuit of  claim 6  wherein the controller circuitry is configured to continuously make determinations of whether to adjust the negative voltage in connection with the adequate minimization of the static leakage. 
     
     
       8. The integrated circuit of  claim 6  wherein the controller circuitry is configured to periodically make determinations of whether to adjust the negative voltage in connection with the adequate minimization of the static leakage. 
     
     
       9. The integrated circuit of  claim 6  wherein the voltage generator is configured to selectively generate the negative voltage. 
     
     
       10. The integrated circuit of  claim 6  wherein the voltage generator is a charge pump. 
     
     
       11. An integrated circuit comprising:
 a logic component, the logic component being either a logic gate or a storage cell, and the logic component including a sleep transistor in series with an electrical connection to a ground terminal;   a voltage generator configured to generate a negative voltage to be applied to the sleep transistor; and   controller circuitry configured to:   i) induce a current through an emulated sleep transistor in proportion to a static leakage of the integrated circuit;   ii) make a determination of whether to adjust the negative voltage depending on the amount of the current; and   iii) adjust the negative voltage depending on the determination.   
     
     
       12. The integrated circuit of  claim 11  wherein the controller circuitry is configured to continuously make determinations of whether to adjust the negative voltage. 
     
     
       13. The integrated circuit of  claim 11  wherein the controller circuitry is configured to periodically make determinations of whether to adjust the negative voltage. 
     
     
       14. The integrated circuit of  claim 11  wherein the voltage generator is configured to selectively generate the negative voltage. 
     
     
       15. The integrated circuit of  claim 11  wherein the voltage generator is a charge pump. 
     
     
       16. An integrated circuit comprising:
 a logic component, the logic component being either a logic gate or a storage cell, and the logic component including a sleep transistor in series with an electrical connection to a ground terminal;   a voltage generator configured to generate a negative voltage to be applied to the sleep transistor; and   a controller configured to receive the negative voltage and determine whether to adjust the negative voltage based on a comparison of a first current and a second current, the controller including:   i) a first transistor configured to receive the negative voltage that defines the first current through the first transistor;   ii) a second transistor configured to receive the negative voltage plus an offset voltage that define the second current through the second transistor; and   iii) circuitry configured to compare the first current to the second current.   
     
     
       17. The integrated circuit of  claim 16  wherein the first and second transistors are emulated sleep transistors. 
     
     
       18. The integrated circuit of  claim 17  wherein the voltage generator is configured to selectively generate the negative voltage. 
     
     
       19. The integrated circuit of  claim 16  wherein the controller is configured to continuously determine whether to adjust the negative voltage. 
     
     
       20. The integrated circuit of  claim 16  wherein the controller is configured to periodically determine whether to adjust the negative voltage. 
     
     
       21. The integrated circuit of  claim 16  wherein the voltage generator is configured to selectively generate the negative voltage. 
     
     
       22. The integrated circuit of  claim 21  wherein the voltage generator is a charge pump. 
     
     
       23. The integrated circuit of  claim 16  wherein the voltage generator is a charge pump. 
     
     
       24. An integrated circuit comprising:
 two power supply terminals configured to power the integrated circuit, said power supply terminals including a V dd  positive supply terminal and a V ss  ground terminal together defining a range of logic levels;   a logic component, the logic component being either a logic gate or a storage cell;   a sleep transistor in series with the logic component and an electrical connection to one of said power supply terminals;   a voltage generator configured to selectively generate a voltage outside said range of logic levels for application to said sleep transistor during a power down mode, and another voltage outside the range of logic levels for application to said sleep transistor when in a mode other than said power down mode, responsive to an enable signal; and   a control circuit configured to control said voltage generator to adequately minimize leakage current through said sleep transistor during said power down mode, comprising:
 a first voltage divider configured to provide a voltage reference; 
 a second voltage divider configured to provide a variable voltage reference responsive to said voltage outside said range of logic levels; and 
 a comparator having a first input coupled to receive the voltage reference from the first voltage divider, a second input coupled to receive the variable voltage reference from the second voltage divider, and an output coupled to provide the enable signal to the voltage generator.  
   
     
     
       25. The integrated circuit as claimed in claim 24 wherein said one of said power supply terminals is the V SS  terminal, said voltage outside the range of logic levels is a voltage lower than V SS , and said sleep transistor is an n-channel transistor.  
     
     
       26. The integrated circuit as claimed in claim 24 wherein said logic gate is one of an inverter, a NAND, NOR, exclusive-OR, and exclusive-NOR gate.  
     
     
       27. The integrated circuit as claimed in claim 24 wherein said storage cell is one of a flip-flop and a latch.  
     
     
       28. The integrated circuit as claimed in claim 24 wherein said voltage generator comprises a charge pump circuit.  
     
     
       29. The integrated circuit as claimed in claim 24 wherein said control circuit includes an emulated sleep transistor configured to be biased at said voltage outside the range of logic levels;
 wherein the voltage reference provided by the first voltage divider is a fixed voltage reference;   and wherein the second voltage divider comprises a variable resistor controlled in response to current conducted by the emulated sleep transistor.    
     
     
       30. The integrated circuit as claimed in claim 29 wherein the emulated sleep transistor corresponds to a first emulated sleep transistor;
 and wherein the control circuit further comprises:
 a second emulated sleep transistor configured to be biased at said voltage outside the range of logic levels with a voltage offset; and 
 a differential amplifier, having a first input coupled to the first emulated sleep transistor, a second input coupled to the second emulated sleep transistor, and an output coupled to the variable resistor of the second voltage divider.  
   
     
     
       31. The integrated circuit as claimed in claim 30 wherein said control circuit is configured to control the voltage generator to adjust said voltage outside the range of logic levels to equalize currents conducted through said first and second emulated sleep transistors.  
     
     
       32. The integrated circuit as claimed in claim 24 wherein said sleep transistor has a similar threshold voltage as other transistors in said logic components.  
     
     
       33. The integrated circuit as claimed in claim 32 wherein said sleep transistor is a low threshold voltage transistor.