Data processing device and data processing method

Abstract

The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 6/15, 8/15, or 10/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.

The invention claimed is: 
     
       1. A data processing device comprising:
 an encoding unit configured to perform LDPC encoding based on a parity check matrix of an LDPC code in which a code length N is 16200 bits and an encoding rate r is 6/15;   a group-wise interleaving unit configured to perform group-wise interleave of interleaving the LDPC code in units of bit groups of 360 bits; and   a mapping unit configured to map the LDPC code to any of 4 signal points decided in a modulation scheme in units of 2 bits, wherein   in the group-wise interleave, when an (i+1)-th bit group from a head of the LDPC code is indicated by a bit group i, a sequence of bit groups 0 to 44 of the LDPC code of 16200 bits is interleaved into a sequence of bit groups   21, 41, 15, 29, 0, 23, 16, 12, 38, 43, 2, 3, 4, 20, 31, 27, 5, 33, 28, 30, 36, 8, 40, 13, 6, 9, 18, 24, 7, 39, 10, 17, 37, 1, 19, 22, 25, 26, 14, 32, 34, 11, 35, 42, and 44,   the LDPC code includes an information bit and a parity bit,   the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit,   the information matrix portion is represented by a parity check matrix initial value table, and   the parity check matrix initial value table is a table in which a position of a 1 element of the information matrix portion is indicated for every 360 columns, and includes   27 430 519 828 1897 1943 2513 2600 2640 3310 3415 4266 5044 5100 5328 5483 5928 6204 6392 6416 6602 7019 7415 7623 8112 8485 8724 8994 9445 9667   27 174 188 631 1172 1427 1779 2217 2270 2601 2813 3196 3582 3895 3908 3948 4463 4955 5120 5809 5988 6478 6604 7096 7673 7735 7795 8925 9613 9670   27 370 617 852 910 1030 1326 1521 1606 2118 2248 2909 3214 3413 3623 3742 3752 4317 4694 5300 5687 6039 6100 6232 6491 6621 6860 7304 8542 8634   990 1753 7635 8540   933 1415 5666 8745   27 6567 8707 9216   2341 8692 9580 9615   260 1092 5839 6080   352 3750 4847 7726   4610 6580 9506 9597   2512 2974 4814 9348   1461 4021 5060 7009   1796 2883 5553 8306   1249 5422 7057   3965 6968 9422   1498 2931 5092   27 1090 6216   26 4232 6354.   
     
     
       2. A receiving device comprising:
 a receiver configured to receive a digital broadcast signal including a mapped group-wise interleaved low density parity check (LDPC) code word; and   circuitry configured to
 process the mapped group-wise interleaved LDPC code word to obtain a group-wise interleaved LDPC code word, wherein each unit of two bits of the group-wise interleaved LDPC code word is mapped to one of 4 signal points of a first modulation scheme, 
 process the group-wise interleaved LDPC code word to obtain an LDPC code word of an LDPC code, the group-wise interleaved LDPC code word has a following sequence of bit groups: 
 1, 4, 5, 6, 24, 21, 18, 7, 17, 12, 8, 20, 23, 29, 28, 30, 32, 34, 36, 38, 40, 42, 0, 2, 3, 14, 22, 13, 10, 25, 9, 27, 19, 16, 15, 26, 11, 31, 33, 35, 37, 39, 41, 43, and 44, 
   decode the LDPC code word of the LDPC code to obtain a decoded LDPC code word, and process the decoded LDPC code word for presentation of the digital broadcast signal,   wherein
 the LDPC code has a code length N of 16200 bits and a code rate r of 10/15.  
   
     
     
       3. The receiving device according to claim 2, wherein the LDPC code is based on a parity check matrix initial value table listed as follows:
 352 747 894 1437 1688 1807 1883 2119 2159 3321 3400 3543 3588 3770 3821 4384 4470 4884 5012 5036 5084 5101 5271 5281 5353   505 915 1156 1269 1518 1650 2153 2256 2344 2465 2509 2867 2875 3007 3254 3519 3687 4331 4439 4532 4940 5011 5076 5113 5367   268 346 650 919 1260 4389 4653 4721 4838 5054 5157 5162 5275 5362   220 236 828 1590 1792 3259 3647 4276 4281 4325 4963 4974 5003 5037   381 737 1099 1409 2364 2955 3228 3341 3473 3985 4257 4730 5173 5242   88 771 1640 1737 1803 2408 2575 2974 3167 3464 3780 4501 4901 5047   749 1502 2201 3189   2873 3245 3427   2158 2605 3165   1 3438 3606   10 3019 5221   371 2901 2923   9 3935 4683   1937 3502 3735   507 3128 4994   25 3854 4550   1178 4737 5366   2 223 5304   1146 5175 5197   1816 2313 3649   740 1951 3844   1320 3703 4791   1754 2905 4058   7 917 5277   3048 3954 5396   4804 4824 5105   2812 3895 5226   0 5318 5358   1483 2324 4826   2266 4752 5387.    
     
     
       4. The receiving device according to claim 2, wherein
 the LDPC code word of the LDPC code is encoded based on a parity check matrix of the LDPC code,   the parity check matrix includes an information matrix part corresponding to information bits and a parity matrix part corresponding to parity bits,   the information matrix part being represented by a parity check matrix initial value table, and   each row of the parity check matrix initial value table indicates positions of elements “1” in corresponding 360 columns of the information matrix part corresponding to a subset of information bits used in calculating the parity bits.    
     
     
       5. The receiving device according to claim 4, wherein
 if a row of the parity check matrix initial value table is represented by I and a length of the parity bits of the LDPC code word of the LDPC code is represented by M, the 2+360×(i−1)-th column of the parity check matrix is obtained by the cyclic shift of the LDPC code word of the LDPC code is encoded based on a parity check matrix of the LDPC code,   the parity check matrix includes an information matrix part corresponding to information bits and a parity matrix part corresponding to parity bits,   the information matrix part being represented by a parity check matrix initial value table, and   each row of the parity check matrix initial value table indicates positions of elements “1” in corresponding 360 columns of the information matrix part corresponding to a subset of information bits used in calculating the parity bits.    
     
     
       6. A method for use by a receiving device, the method comprising:
 receiving a digital broadcast signal including a mapped group-wise interleaved low density parity check (LDPC) code word;   processing the mapped group-wise interleaved LDPC code word to obtain a group-wise interleaved LDPC code word, wherein each unit of two bits of the group-wise interleaved LDPC code word is mapped to one of 4 signal points of a first modulation scheme,   processing the group-wise interleaved LDPC code word to obtain an LDPC code word of an LDPC code, the group-wise interleaved LDPC code word has a following sequence of bit groups:
 1, 4, 5, 6, 24, 21, 18, 7, 17, 12, 8, 20, 23, 29, 28, 30, 32, 34, 36, 38, 40, 42, 0, 2, 3, 14, 22, 13, 10, 25, 9, 27, 19, 16, 15, 26, 11, 31, 33, 35, 37, 39, 41, 43, and 44, 
   decoding the LDPC code word of the LDPC code to obtain a decoded LDPC code word, and   processing the decoded LDPC code word for presentation of the digital broadcast signal,   wherein
 the LDPC code has a code length N of 16200 bits and a code rate r of 10/15.  
   
     
     
       7. The method according to claim 6, wherein the LDPC code is based on a parity check matrix initial value table listed as follows:
 352 747 894 1437 1688 1807 1883 2119 2159 3321 3400 3543 3588 3770 3821 4384 4470 4884 5012 5036 5084 5101 5271 5281 5353   505 915 1156 1269 1518 1650 2153 2256 2344 2465 2509 2867 2875 3007 3254 3519 3687 4331 4439 4532 4940 5011 5076 5113 5367   268 346 650 919 1260 4389 4653 4721 4838 5054 5157 5162 5275 5362   220 236 828 1590 1792 3259 3647 4276 4281 4325 4963 4974 5003 5037   81 737 1099 1409 2364 2955 3228 3341 3473 3985 4257 4730 5173 5242   88 771 1640 1737 1803 2408 2575 2974 3167 3464 3780 4501 4901 5047   749 1502 2201 3189   2873 3245 3427   2158 2605 3165   1 3438 3606   10 3019 5221   371 2901 2923   9 3935 4683   1937 3502 3735   507 3128 4994   25 3854 4550   1178 4737 5366   2 223 5304   1146 5175 5197   1816 2313 3649   740 1951 3844   1320 3703 4791   1754 2905 4058   7 917 5277   3048 3954 5396   4804 4824 5105   2812 3895 5226   0 5318 5358   1483 2324 4826   2266 4752 5387.    
     
     
       8. The method according to claim 6, wherein
 the LDPC code word of the LDPC code is encoded based on a parity check matrix of the LDPC code,   the parity check matrix includes an information matrix part corresponding to information bits and a parity matrix part corresponding to parity bits,   the information matrix part being represented by a parity check matrix initial value table, and   each row of the parity check matrix initial value table indicates positions of elements “1” in corresponding 360 columns of the information matrix part corresponding to a subset of information bits used in calculating the parity bits.    
     
     
       9. The receiving device according to claim 8, wherein
 if a row of the parity check matrix initial value table is represented by I and a length of the parity bits of the LDPC code word of the LDPC code is represented by M, the 2+360×(i−1)-th column of the parity check matrix is obtained by the cyclic shift of the LDPC code word of the LDPC code is encoded based on a parity check matrix of the LDPC code,   the parity check matrix includes an information matrix part corresponding to information bits and a parity matrix part corresponding to parity bits,   the information matrix part being represented by a parity check matrix initial value table, and   each row of the parity check matrix initial value table indicates positions of elements “1” in corresponding 360 columns of the information matrix part corresponding to a subset of information bits used in calculating the parity bits.