USRE50103EActiveUtility

Circuits for a hybrid switched capacitor converter

59
Assignee: LION SEMICONDUCTOR INCPriority: Apr 14, 2017Filed: Jan 18, 2022Granted: Aug 27, 2024
Est. expiryApr 14, 2037(~10.8 yrs left)· nominal 20-yr term from priority
Inventors:Alberto Alessandro Angelo PuggelliThomas LiWonyoung KimJohn CrossleyHanh-Phuc Le
H02M 3/077H02M 1/007H02M 3/072H02M 5/32H02M 3/335H02M 3/1588H02M 3/158H02M 3/157H02M 1/0045H02M 3/07
59
PatentIndex Score
0
Cited by
91
References
31
Claims

Abstract

Circuits comprising: an inductor having a first side connected to VIN; a first switch having a first side connected to a second side of the inductor; a second switch having a first side connected to VIN; a first capacitor having a first side connected to a second side of the second switch; a third switch having a first side connected to a second side of the first switch; a fourth switch having a first side connected to a second side of the third switch; a fifth switch having a first side connected to a second side of the first capacitor and to a second side of the fourth switch, and having a second side coupled to a voltage source; and a second capacitor having a first side connected to the first side of the fourth switch, and having a second side connected to the second side of the fifth switch.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A circuit, comprising:
 an inductor having a first side and a second side, wherein the first side is connected to an input voltage; 
 a first switch having a first side and a second side, wherein the first side is connected to the second side of the inductor; 
 a second switch having a first side and a second side, wherein the first side is connected to the input voltage; 
 a first capacitor having a first side and a second side, wherein the first side is connected to the second side of the second switch; 
 a third switch having a first side and a second side, wherein the first side is connected to the second side of the first switch; 
 a fourth switch having a first side and a second side, wherein the first side is connected to the second side of the third switch; 
 a fifth switch having a first side and a second side, wherein the first side is connected to the second side of the first capacitor and to the second side of the fourth switch, and wherein the second side is coupled to a voltage source; and 
 a second capacitor having a first side and a second side, wherein the first side is connected to the first side of the fourth switch, and wherein the second side is connected to the second side of the fifth switch. 
 
     
     
       2. The circuit of  claim 1 , wherein at least one of the first switch, the second switch, the third switch, the fourth switch, and the fifth switch is a transistor. 
     
     
       3. The circuit of  claim 2 , wherein at least one of the first switch, the second switch, the third switch, the fourth switch, and the fifth switch is a MOSFET. 
     
     
       4. The circuit of  claim 2 , wherein the at least one of the first switch, the second switch, the third switch, the fourth switch, and the fifth switch is controlled by a controller. 
     
     
       5. The circuit of  claim 1 , further comprising a controller, wherein:
 when the circuit is in a first state, the controller causes:
 the first switch is to be closed; 
 the second switch is to be open; 
 the third switch is to be open; 
 the fourth switch is to be closed; and 
 the fifth switch is to be open; and 
 
 when the circuit is in a second state, the controller causes:
 the first switch is to be closed; 
 the second switch is to be open; 
 the third switch is to be closed; 
 the fourth switch is to be open; and 
 the fifth switch is to be closed. 
 
 
     
     
       6. The circuit of  claim 5 , wherein:
 when the circuit is in a third state, the controller causes:
 the first switch is to be open; 
 the second switch is to be closed; 
 the third switch is to be open; 
 the fourth switch is to be closed; and 
 the fifth switch is to be open; and 
 
 when the circuit is in a fourth state, the controller causes:
 the first switch is to be open; 
 the second switch is to be open; 
 the third switch is to be closed; 
 the fourth switch is to be open; and 
 the fifth switch is to be closed. 
 
 
     
     
       7. The circuit of  claim 1 , further comprising:
 a sixth switch having a first side and a second side, wherein the first side is connected to the second side of the inductor; 
 a seventh switch having a first side and a second side, wherein the first side is connected to the input voltage; 
 a third capacitor having a first side and a second side, wherein the first side is connected to the second side of the seventh switch; 
 aan eighth switch having a first side and a second side, wherein the first side is connected to the second side of the sixth switch; 
 a ninth switch having a first side and a second side, wherein the first side is connected to the second side of the eighth switch; and 
 a tenth switch having a first side and a second side, wherein the first side is connected to the second side of the third capacitor and to the second side of the ninth switch, and wherein the second side is coupled to the voltage source. 
 
     
     
       8. The circuit of  claim 7 , wherein:
 when the circuit is in a first state, the controller causes:
 the first switch is to be open; 
 the second switch is to be closed; 
 the third switch is to be open; 
 the fourth switch is to be closed; 
 the fifth switch is to be open; 
 the sixth switch is to be open; 
 the seventh switch is to be open; 
 the eighth switch is to be closed; 
 the ninth switch is to be open; and 
 the tenth switch is to be closed; and 
 
 when the circuit is in a second state, the controller causes:
 the first switch is to be open; 
 the second switch is to be open; 
 the third switch is to be closed; 
 the fourth switch is to be open; 
 the fifth switch is to be closed; 
 the sixth switch is to be open; 
 the seventh switch is to be closed; 
 the eighth switch is to be open; 
 the ninth switch is to be closed; and 
 the tenth switch is to be open. 
 
 
     
     
       9. The circuit of  claim 8 , wherein:
 when the circuit is in a third state, the controller causes:
 the first switch is to be closed; 
 the second switch is to be open; 
 the third switch is to be open; 
 the fourth switch is to be closed; 
 the fifth switch is to be open; 
 the sixth switch is to be open; 
 the seventh switch is to be open; 
 the eighth switch is to be closed; 
 the ninth switch is to be open; and 
 the tenth switch is to be closed; 
 
 when the circuit is in a fourth state, the controller causes:
 the first switch is to be open; 
 the second switch is to be open; 
 the third switch is to be open; 
 the fourth switch is to be closed; 
 the fifth switch is to be open; 
 the sixth switch is to be closed; 
 the seventh switch is to be open; 
 the eighth switch is to be closed; 
 the ninth switch is to be open; and 
 the tenth switch is to be closed; 
 
 
       when the circuit is in a fifth state, the controller causes:
 the first switch is to be open; 
 the second switch is to be open; 
 the third switch is to be closed; 
 the fourth switch is to be open; 
 the fifth switch is to be closed; 
 the sixth switch is to be closed; 
 the seventh switch is to be open; 
 the eighth switch is to be open; 
 the ninth switch is to be closed; and 
 the tenth switch is to be open; and 
 
       when the circuit is in a sixth state, the controller causes:
 the first switch is to be closed; 
 the second switch is to be open; 
 the third switch is to be closed; 
 the fourth switch is to be open; 
 the fifth switch is to be closed; 
 the sixth switch is to be open; 
 the seventh switch is to be open; 
 the eighth switch is to be open; 
 the ninth switch is to be closed; and 
 the tenth switch is to be open. 
 
     
     
       10. The circuit of  claim 1 , wherein the second side of the second switch is connected to the second side of the first switch. 
     
     
       11. The circuit of  claim 7 , wherein the second side of the seventh switch is connected to the second side of the sixth switch. 
     
     
       12. The circuit of  claim 1 , wherein the first capacitor is implemented on-chip. 
     
     
       13. The circuit of  claim 12 , wherein the first capacitor is one of:
 a metal-on-metal (MoM) on-chip capacitor;   a metal-insulator-metal (MiM) on-chip capacitor; and   a MOSFET on-chip capacitor.   
     
     
       14. The circuit of  claim 1 , wherein the first capacitor is implemented on a circuit board. 
     
     
       15. The circuit of  claim 14 , wherein the first capacitor is one of:
 a multi-layer ceramic capacitor;   a tantalum capacitor;   an aluminum electrolytic capacitor; and   a film capacitor.   
     
     
       16. The circuit of  claim 1 , wherein the inductor is a discrete inductor. 
     
     
       17. A circuit, comprising:
 an inductor having a first side and a second side, wherein the first side is connected to an input voltage node;   a first switch having a first side and a second side, wherein the first side of the first switch is connected to the second side of the inductor;   a second switch having a first side and a second side, wherein the first side of the second switch is connected to the first side of the inductor, and wherein the second side of the second switch is connected to the second side of the first switch;   a first capacitor having a first side and a second side, wherein the first side of the first capacitor is connected to the second side of the second switch;   a third switch having a first side and a second side, wherein the first side of the third switch is connected to the second side of the first switch;   a fourth switch having a first side and a second side, wherein the first side of the fourth switch is connected to the second side of the third switch;   a fifth switch having a first side and a second side, wherein the first side of the fifth switch is connected to the second side of the first capacitor and to the second side of the fourth switch, and wherein the second side is coupled to a voltage source node; and   a second capacitor having a first side and a second side, wherein the first side is connected to the first side of the fourth switch, and wherein the second side is connected to the second side of the fifth switch.   
     
     
       18. The circuit of  claim 17 , wherein the inductor is a discrete inductor. 
     
     
       19. The circuit of  claim 17 , wherein at least one of the first switch, the second switch, the third switch, the fourth switch, and the fifth switch is a transistor. 
     
     
       20. The circuit of  claim 19 , wherein at least one of the first switch, the second switch, the third switch, the fourth switch, and the fifth switch is a MOSFET. 
     
     
       21. The circuit of  claim 19 , wherein the at least one of the first switch, the second switch, the third switch, the fourth switch, and the fifth switch is controlled by a controller. 
     
     
       22. The circuit of  claim 17 , further comprising a controller, wherein:
 when the circuit is powered and in a first state, the controller causes:
 the first switch to be closed; 
 the second switch to be open; 
 the third switch to be open; 
 the fourth switch to be closed; and 
 the fifth switch to be open; and 
   when the circuit is powered and is in a second state, the controller causes:
 the first switch to be closed; 
 the second switch to be open; 
 the third switch to be closed; 
 the fourth switch to be open; and 
 the fifth switch to be closed. 
   
     
     
       23. The circuit of  claim 22 , wherein:
 when the circuit is powered and is in a third state, the controller causes:
 the first switch to be open; 
 the second switch to be closed; 
 the third switch to be open; 
 the fourth switch to be closed; and 
 the fifth switch to be open; and 
   when the circuit is powered and is in a fourth state, the controller causes:
 the first switch to be open; 
 the second switch to be open; 
 the third switch to be closed; 
 the fourth switch to be open; and 
 the fifth switch to be closed. 
   
     
     
       24. The circuit of  claim 17 , the circuit further comprising:
 a third capacitor having a first side and a second side;   a sixth switch having a first side and a second side, wherein the first side of the sixth switch is connected to the first side of the first switch;   a seventh switch having a first side and a second side, wherein the first side of the seventh switch is connected to the input voltage node, wherein the second side of the seventh switch is connected to the second side of the sixth switch, and wherein the second side of the seventh switch is connected to first side of the third capacitor;   an eighth switch having a first side and a second side, wherein the first side of the eighth switch is connected to the second side of the sixth switch;   a ninth switch having a first side and a second side, wherein the first side of the ninth switch is connected to the second side of the eighth switch; and   a tenth switch having a first side and a second side, wherein the first side of the tenth switch is connected to the second side of the ninth switch, and wherein the first side of the tenth switch is connected to the second side of the third capacitor.   
     
     
       25. The circuit of  claim 24 , wherein the second side of the tenth switch is connected to the voltage source node. 
     
     
       26. The circuit of  claim 24 , wherein:
 when the circuit is powered and is in a first state, the controller causes:
 the first switch to be open; 
 the second switch to be closed; 
 the third switch to be open; 
 the fourth switch to be closed; 
 the fifth switch to be open; 
 the sixth switch to be open; 
 the seventh switch to be open; 
 the eighth switch to be closed; 
 the ninth switch to be open; and 
 the tenth switch to be closed; and 
   when the circuit is powered and is in a second state, the controller causes:
 the first switch to be open; 
 the second switch to be open; 
 the third switch to be closed; 
 the fourth switch to be open; 
 the fifth switch to be closed; 
 the sixth switch to be open; 
 the seventh switch to be closed; 
 the eighth switch to be open; 
 the ninth switch to be closed; and 
 the tenth switch to be open. 
   
     
     
       27. The circuit of  claim 26 , wherein:
 when the circuit is powered and is in a third state, the controller causes:
 the first switch to be closed; 
 the second switch to be open; 
 the third switch to be open; 
 the fourth switch to be closed; 
 the fifth switch to be open; 
 the sixth switch to be open; 
 the seventh switch to be open; 
 the eighth switch to be closed; 
 the ninth switch to be open; and 
 the tenth switch to be closed; 
   when the circuit is powered and is in a fourth state, the controller causes:
 the first switch to be open; 
 the second switch to be open; 
 the third switch to be open; 
 the fourth switch to be closed; 
 the fifth switch to be open; 
 the sixth switch to be closed; 
 the seventh switch to be open; 
 the eighth switch to be closed; 
 the ninth switch to be open; and 
 the tenth switch to be closed; 
   when the circuit is powered and is in a fifth state, the controller causes:
 the first switch to be open; 
 the second switch to be open; 
 the third switch to be closed; 
 the fourth switch to be open; 
 the fifth switch to be closed; 
 the sixth switch to be closed; 
 the seventh switch to be open; 
 the eighth switch to be open; 
 the ninth switch to be closed; and 
 the tenth switch to be open; and 
   when the circuit is powered and is in a sixth state, the controller causes:
 the first switch to be closed; 
 the second switch to be open; 
 the third switch to be closed; 
 the fourth switch to be open; 
 the fifth switch to be closed; 
 the sixth switch to be open; 
 the seventh switch to be open; 
 the eighth switch to be open; 
 the ninth switch to be closed; and 
 the tenth switch to be open. 
   
     
     
       28. The circuit of  claim 17 , wherein the first capacitor is implemented on-chip. 
     
     
       29. The circuit of  claim 28 , wherein the first capacitor is one of:
 a metal-on-metal (MoM) on-chip capacitor;   a metal-insulator-metal (MiM) on-chip capacitor; and   a MOSFET on-chip capacitor.   
     
     
       30. The circuit of  claim 17 , wherein the first capacitor is implemented on a circuit board. 
     
     
       31. The circuit of  claim 30 , wherein the first capacitor is one of:
 a multi-layer ceramic capacitor;   a tantalum capacitor;   an aluminum electrolytic capacitor; and   a film capacitor.

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