Computing system with adaptive back-up mechanism and method of operation thereof

Abstract

A computing system includes: an adaptive back-up controller configured to calculate an adaptive back-up time based on a reserve power source for backing up a volatile memory to a nonvolatile memory; and a processor core, coupled to the adaptive back-up controller, configured to back up at least a portion of the volatile memory to the nonvolatile memory within the adaptive back-up time based on a back-up priority.

What is claimed is: 
     
       1. A computing system memory module comprising:
 a storage card configured to transfer data that includes:  an adaptive back-up controller, connected to the storage card, configured to calculate an adaptive back-up time based on a reserve power source for backing up a volatile memory to a nonvolatile memory, and   adjust a power state of data reliability circuitry, by lowering power consumption to only leakage current in functions for error detection, error correction, or a combination thereof, to change the adaptive back-up time to an adjusted adaptive back-up time; and   
 a processor core, on the storage card and coupled to the adaptive back-up controller, configured to back up at least a portion of the volatile memory to the nonvolatile memory within the adjusted adaptive back-up time based on a back-up priority. 
 
     
     
       2. The system memory module as claimed in  claim 1  wherein the adaptive back-up controller is further configured to adjust the adaptive back-up time based on a change to the reserve power source. 
     
     
       3. The system memory module as claimed in  claim 1  wherein the adaptive back-up controller is further configured to calculate an available back-up time for the reserve power source based on stopping storage system maintenance functions and blocking a clock for the data reliability circuitry. 
     
     
       4. The system memory module as claimed in  claim 1  wherein:
 the adaptive back-up controller is further configured to calculate a write entries commit from the volatile memory to back-up volatile data functioning as a cache data based on the back-up priority; and 
 the processor core is further configured to back-up the write entries commit. 
 
     
     
       5. The system memory module as claimed in  claim 1  wherein:
 the adaptive back-up controller is further configured to adjust a write entries commit from the volatile memory to back-up volatile data functioning as a cache data based on the back-up priority selecting dirty data from the cache data; and 
 the processor core is further configured to back-up the write entries commit for the dirty data. 
 
     
     
       6. The system memory module as claimed in  claim 1  wherein the adaptive back-up controller is further configured to calculate a write entries commit, based on a nonvolatile latency and a nonvolatile bandwidth, from the volatile memory to back-up. 
     
     
       7. The system memory module as claimed in  claim 1  wherein:
 the adaptive back-up controller is further configured to adjust the adaptive back-up time based on a change to the reserve power source; and 
 the processor core is further configured to adjust a write entries commit, based on the adaptive back-up time, from the volatile memory to back-up. 
 
     
     
       8. The system memory module as claimed in  claim 1  further comprising:
 a power detector, coupled to the processor core, configured to detect a power failure; and 
 a power saving path, coupled to the processor core, configured to back-up the portion of the volatile memory to the nonvolatile memory based on the power failure. 
 
     
     
       9. The system memory module as claimed in  claim 1  further comprising:
 a power detector, coupled to the processor core, configured to detect a power failure; 
 a program mode circuitry, coupled to the processor core, configured to program a faster write mode for writing to the nonvolatile memory; and 
 
       wherein:
 the processor core is further configured to back-up the portion of the volatile memory to the nonvolatile memory with the faster write mode based on the power failure. 
 
     
     
       10. The system memory module as claimed in  claim 1  further comprising:
 a power detector, coupled to the processor core, configured to detect a power failure; 
 
       wherein:
 the processor core is further configured to modify a data transfer mode for the volatile memory to back-up the portion of the volatile memory to the nonvolatile memory based on the power failure. 
 
     
     
       11. A method of operation of a computing system memory module comprising:
 calculating an adaptive back-up time based on a reserve power source for backing up a volatile memory to a nonvolatile memory; 
 adjusting a power state of data reliability circuitry, by lowering power consumption to only leakage current in functions for error detection, error correction, or a combination thereof, to change the adaptive back-up time to an adjusted adaptive back-up time; and 
 backing up at least a portion of the volatile memory to the nonvolatile memory within the adjusted adaptive back-up time based on a back-up priority. 
 
     
     
       12. The method as claimed in  claim 11  wherein calculating the adaptive back-up time includes adjusting the adaptive back-up time based on a change to the reserve power source. 
     
     
       13. The method as claimed in  claim 11  wherein calculating the adaptive back-up time based on the reserve power source includes calculating an available back-up time for the reserve power source based on stopping storage system maintenance functions and blocking a clock for the data reliability circuitry. 
     
     
       14. The method as claimed in  claim 11  further comprising:
 calculating a write entries commit from the volatile memory to back-up volatile data functioning as a cache data based on the back-up priority; and 
 
       wherein:
 backing up at least the portion of the volatile memory includes backing up the write entries commit. 
 
     
     
       15. The method as claimed in  claim 11  further comprising:
 adjusting a write entries commit from the volatile memory to back-up volatile data functioning as a cache data based on the back-up priority selecting dirty data from the cache data; and 
 
       wherein:
 backing up at least a portion of the volatile memory to the nonvolatile memory within the adaptive back-up time includes backing up the write entries commit for the dirty data. 
 
     
     
       16. The method as claimed in  claim 11  wherein backing up at least a portion of the volatile memory to the nonvolatile memory within the adaptive back-up time includes calculating a write entries commit, based on a nonvolatile latency and a nonvolatile bandwidth, from the volatile memory to back-up. 
     
     
       17. The method as claimed in  claim 11  wherein:
 calculating the adaptive back-up time includes adjusting the adaptive back-up time based on a change to the reserve power source; and 
 backing up at least a portion of the volatile memory to the nonvolatile memory within the adaptive back-up time includes adjusting a write entries commit, based on the adaptive back-up time, from the volatile memory to back-up. 
 
     
     
       18. The method as claimed in  claim 11  further comprising:
 detecting a power failure; and 
 backing up the portion of the volatile memory to the nonvolatile memory based on the power failure and through a power saving path. 
 
     
     
       19. The method as claimed in  claim 11  further comprising:
 detecting a power failure; 
 programming a faster write mode for writing to the nonvolatile memory; and 
 backing up the portion of the volatile memory to the nonvolatile memory with the faster write mode based on the power failure. 
 
     
     
       20. The method as claimed in  claim 11  further comprising:
 detecting a power failure; and 
 modifying a data transfer mode for the volatile memory to back-up the portion of the volatile memory to the nonvolatile memory based on the power failure.