Buffer circuit, semiconductor integrated circuit device, oscillator, electronic apparatus, and base station

Abstract

A buffer circuit includes a first MOSFET including a first source electrode, a first gate electrode, and a first drain electrode, and a second MOSFET, which includes a second source electrode, a second gate electrode, and a second drain electrode, and is same in polarity as the first MOSFET, and the first gate electrode and the second gate electrode are electrically connected to each other.

What is claimed is: 
     
       1. A buffer circuit comprising:
 a first MOSFET comprising a first source electrode, a first gate electrode, and a first shared drain electrode; 
 a second MOSFET, which comprises a second source electrode, a second gate electrode, and a second drain electrode, and is same in polarity as the first MOSFET, the second gate electrode being electrically connected to the first gate electrode; 
 a third MOSFET comprising a third source electrode, a third gate electrode, and the first shared drain electrode; and 
 a first switch connected to the third first gate electrode and the first second gate electrode; and 
 a second switch connected to the third gate electrode, 
 wherein the first MOSFET and the third MOSFET are same in polarity as each other. 
 
     
     
       2. The buffer circuit according to  claim 1 , wherein
 the first shared drain electrode and the second drain electrode are electrically connected to each other with a common interconnection. 
 
     
     
       3. The buffer circuit according to  claim 1 , wherein
 the first MOSFET and the third MOSFET are same in polarity as each other.   
     
     
       4. The buffer circuit according to  claim 1 , further comprising:
 a second switch connected to the second gate electrode.   
     
     
       5. A buffer circuit comprising:
 at least two MOSFETs comprising a first MOSFET and a second MOSFET; and   an interconnection through which a signal from the MOSFET is transmitted,   wherein a ratio of a sum of widths of parts to be current paths out of the interconnections, in a second state in which the first MOSFET and the second MOSFET are selected, to a sum of widths of parts to be current paths out of the interconnections in a first state, in which the first MOSFET is selected and the second MOSFET is unselected, is lower than a ratio of a sum of a channel width of the first MOSFET and a channel width of the second MOSFET in the second state to a sum of channel widths of the first MOSFET in the first state.   
     
     
       6. The buffer circuit according to  claim 5 , wherein
 the sum of the widths of the parts to be the current paths out of the interconnections is kept substantially constant between the first state and the second state.   
     
     
       7. A buffer circuit comprising:
 a first MOSFET comprising a first source electrode, a first gate electrode, and a first drain electrode;   a second MOSFET, which comprises a second source electrode, a second gate electrode, and a second drain electrode, and is same in polarity as the first MOSFET, the second gate electrode being electrically connected to the first gate electrode; and   a frequency divider, which is disposed in an anterior stage of the first and second MOSFETs, and division ratio of which can be selected.   
     
     
       8. A semiconductor integrated circuit device comprising:
 the buffer circuit according to  claim 1 . 
 
     
     
       9. An oscillator comprising:
 an oscillation element that oscillates; 
 an oscillation circuit configured to oscillate the oscillation element and process a signal output by the oscillation element; and 
 the buffer circuit according to  claim 1  that is connected to an output of the oscillation circuit. 
 
     
     
       10. An electronic apparatus comprising:
 the buffer circuit according to  claim 1 . 
 
     
     
       11. A base station comprising:
 the buffer circuit according to  claim 1 . 
 
     
     
       12. A buffer circuit comprising:
 a first MOSFET comprising a first source electrode, a first gate electrode, and a first shared drain electrode; 
 a second MOSFET, which comprises a second source electrode, a second gate electrode, and a second shared drain electrode, and is same in polarity as the first MOSFET, the second gate electrode being electrically connected to the first gate electrode; 
 a third MOSFET comprising a third source electrode, a third gate electrode, and the first shared drain electrode; and 
 a fourth MOSFET comprising a fourth source electrode, a fourth gate electrode, and the second shared drain electrode, 
 wherein the third MOSFET and the fourth MOSFET are same in polarity as each other, 
 the first MOSFET and the third MOSFET are same in polarity as each other, and 
 the third gate electrode and the fourth gate electrode are electrically connected to each other. 
 
     
     
       13. The buffer circuit according to  claim 12 , wherein
 the first MOSFET and the third MOSFET are same in polarity as each other.   
     
     
       14. The buffer circuit according to  claim 12 , wherein
 the third gate electrode and the fourth gate electrode are electrically connected to each other.   
     
     
       15. The buffer circuit according to  claim 12 , further comprising:
 a switch connected to the second gate electrode. 
 
     
     
       16. The buffer circuit according to  claim 15 , wherein
 the second gate electrode is connected to the fourth gate electrode. 
 
     
     
       17. The buffer circuit according to  claim 12 , wherein
 the first shared drain electrode and the second shared drain electrode are electrically connected to each other with a common interconnection. 
 
     
     
       18. A semiconductor integrated circuit device comprising:
 the buffer circuit according to  claim 12 . 
 
     
     
       19. An oscillator comprising:
 an oscillation element that oscillates; 
 an oscillation circuit configured to oscillate the oscillation element and process a signal output by the oscillation element; and 
 the buffer circuit according to  claim 12  that is connected to an output of the oscillation circuit. 
 
     
     
       20. An electronic apparatus comprising:
 the buffer circuit according to  claim 12 . 
 
     
     
       21. The buffer circuit according to  claim 1 , further comprising:
 a frequency divider having a division ratio that can be selected, the frequency divider outputting a signal,   wherein the first MOSFET is configured to receive the signal output by the frequency divider, and   the second MOSFET is configured to receive the signal output by the frequency divider.