Circuits and methods for measuring the output current of a switched capacitor regulator

Abstract

Circuits comprising: a capacitor; switches that, when State0, couple the capacitor in parallel with the load and, when State1, couple the capacitor in series with the load, wherein a first of the switches connects the capacitor to ground when in State0 and wherein a second of the switches connects the capacitor to an input voltage when in State1; a third switch, wherein a first side of the third switch is connected to the capacitor identically to one of the first switch and the second switch (OFWSW), wherein the third switch switches identically to the OFWSW, wherein the third switch is smaller than the OFWSW; a first resistor connected to the second side of the third switch; and a hardware processor that measures a current flowing through the first resistor and estimates the current provided to the load based on the current measured as flowing through the first resistor.

What is claimed is: 
     
       1. A circuit for measuring a current provided to a load comprising
 a capacitor having a first side and a second side; 
 a plurality of switches that, when in a first state, couple the capacitor in parallel with the load and, when in a second state, couple the capacitor in series with the load, wherein a first switch of the plurality of switches has a first side, a second side, and a control input and connects the first side of the capacitor to ground when the plurality of switches are in the first state and wherein a second switch of the plurality of switches has a first side, a second side, and a control input and connects the second side of the capacitor to an input voltage when the plurality of switches are in the second state; 
 a third switch having a first side, a second side, and a control input, wherein the first side of the third switch is connected to the first side of one of the first switch and the second switch, wherein the control input of the third switch is connected to the control input of the one of the first switch and the second switch, and wherein the third switch is smaller than the one of the first switch and the second switch; 
 a first resistor having a first side and a second side, wherein the first side of the first resistor is directly connected to the second side of the third switch; and 
 a hardware processor that measures a current flowing through the first resistor and estimates the current provided to the load based on the current measured as flowing through the first resistor. 
 
     
     
       2. The circuit for measuring a current provided to a load of  claim 1 , wherein the one of the first switch and the second switch is the first switch. 
     
     
       3. The circuit for measuring a current provided to a load of  claim 2 , wherein the first switch and the third switch are NMOS transistors and wherein the second switch is a PMOS transistor. 
     
     
       4. The circuit for measuring a current provided to a load of  claim 2 , wherein the second side of the resistor is connected to ground. 
     
     
       5. The circuit for measuring a current provided to a load of  claim 1 , wherein the one of the first switch and the second switch is the second switch. 
     
     
       6. The circuit for measuring a current provided to a load of  claim 5 , wherein the second switch and the third switch are PMOS transistors and wherein the first switch is an NMOS transistor. 
     
     
       7. The circuit for measuring a current provided to a load of  claim 5 , wherein the second side of the resistor is connected to the input voltage. 
     
     
       8. The circuit for measuring a current provided to a load of  claim 5 , further comprising:
 a fourth switch having a first side, a second side, and a control input, wherein the first side of the fourth switch is connected to the first side of the first switch, wherein the control input of the fourth switch is connected to the control input of the first switch, and wherein the fourth switch is smaller than the first switch; and 
 a second resistor having a first side and a second side, wherein the first side of the second resistor is connected to the second side the fourth switch and wherein the second side of the second resistor is connected to ground, 
 wherein the hardware processor also measures a current flowing through the second resistor and estimates the current provided to the load based on the current measured as flowing through the second resistor. 
 
     
     
       9. The circuit for measuring a current provided to a load of  claim 8 , wherein the hardware processor estimates the current provided to the load based on a combination of the current flowing through the first resistor and the current flowing through the second resistor. 
     
     
       10. The circuit for measuring a current provided to a load of  claim 1 , wherein the third switch has a width that is equal to or smaller than 1/10th of a width of the one of the first switch and the second switch. 
     
     
       11. The circuit for measuring a current provided to a load of  claim 1 , wherein the third switch has a width that is equal to or smaller than 1/100th of a width of the one of the first switch and the second switch. 
     
     
       12. The circuit for measuring a current provided to a load of  claim 1 , wherein the third switch has a width that is equal to or smaller than 1/1000th of a width of the one of the first switch and the second switch. 
     
     
       13. The circuit for measuring a current provided to a load of  claim 1 , further comprising an analog-to-digital converter that measures a voltage at the first side of the first resistor. 
     
     
       14. The circuit for measuring a current provided to a load of  claim 1 , wherein the hardware processor measures the current flowing through the first resistor by determining a voltage across the resistor and dividing the voltage across the resistor by a known value of the resistor. 
     
     
       15. The circuit for measuring a current provided to a load of  claim 1 , wherein the hardware processor estimates the current provided to the load by dividing the current flowing through the first resistor by a percentage of time that the plurality of switches are in the first state when the one of the first switch and the second switch is the first switch and by a percentage of time that the plurality of switches are in the second state when the one of the first switch and the second switch is the second switch. 
     
     
       16. A regulator comprising:
 a plurality of switches, wherein a first switch of the plurality of switches has a first size;   a capacitor;   a second switch having a second size that is smaller than the first size;   a first resistor having one end connected directly to one side of the second switch; and   a hardware processor configured to calculate an output current of the regulator based upon a voltage measured across the first resistor,   wherein the second switch and the first resistor are connected in series, and are collectively in parallel with the first switch, and   wherein, when in a first state, the plurality of switches couple the capacitor in parallel with a load and, when in a second state, the plurality of switches couple the capacitor in series with the load.   
     
     
       17. The circuit of  claim 16 , further comprising an analog-to-digital converter that measures a voltage at the first side of the first resistor. 
     
     
       18. The regulator of  claim 16 , wherein the first switch connects the first side of the capacitor to ground when the plurality of switches are in the first state. 
     
     
       19. The circuit of  claim 18 , wherein the hardware processor also estimates the output current provided to a load by dividing an amount of current flowing through the first resistor by a percentage of time that the plurality of switches are in the first state. 
     
     
       20. The regulator of  claim 16 , wherein the first switch connects the capacitor to an input voltage when the plurality of switches are in the second state. 
     
     
       21. The circuit of  claim 20 , further comprising a hardware processor that estimates the output current provided to a load by dividing an amount of current flowing through the first resistor by a percentage of time that the plurality of switches are in the second state. 
     
     
       22. The regulator of  claim 16 , wherein the plurality of switches includes a third switch having a third size, further comprising:
 a fourth switch having a fourth size that is smaller than the third size; and   a second resistor having one end connected to one side of the fourth switch,   wherein the fourth switch and the second resistor are connected in series, and are collectively in parallel with the third switch, and   wherein the output current of the regulator is estimated based upon voltages measured across the first resistor and the second resistor.   
     
     
       23. The circuit of  claim 16 , wherein the first size and the second size are transistor widths, and wherein the second size is equal to or smaller than 1/10th of the first size. 
     
     
       24. The circuit of  claim 16 , wherein the first size and the second size are transistor widths, and wherein the second size is equal to or smaller than 1/100th of the first size. 
     
     
       25. The circuit of  claim 16 , wherein the first size and the second size are transistor widths, and wherein the second size is equal to or smaller than 1/1000th of the first size.