Semiconductor memory device

Abstract

According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.

What is claimed is: 
     
       1. A semiconductor memory device comprising:
 a first word line provided above a substrate; 
 a second word line provided above the first word line; 
 a first pillar including a first columnar portion, a second columnar portion and a joint portion, the first columnar portion being provided above the substrate, the second columnar portion being provided above the first columnar portion and passing through the first word line and the second word line, and the joint portion being provided between the first columnar portion and the second columnar portion; 
 a row decoder configured to apply a voltage to the first and the second word lines; and 
 a select transistor provided above the first pillar, wherein 
 in a precharge operation performed during a write operation, the row decoder is configured to apply a first voltage to the first word line and to apply a second voltage lower than the first voltage to the second word line. 
 
     
     
       2. The semiconductor memory device according to  claim 1 , further comprising a third word line provided above the second word line, wherein
 in the precharge operation, the row decoder is configured to apply a third voltage lower than the second voltage to the third word line. 
 
     
     
       3. The semiconductor memory device according to  claim 1 , further comprising a fourth word line provided between the first word line and the joint portion, wherein
 in the precharge operation, the row decoder is configured to apply a fourth voltage lower than the first voltage to the fourth word line. 
 
     
     
       4. The semiconductor memory device according to  claim 1 ,
 wherein the write operation includes a program operation performed after the precharge operation, and 
 in the program operation, the row decoder is configured to apply a program voltage to the second word line. 
 
     
     
       5. The semiconductor memory device according to  claim 1 ,
 wherein the first word line and the second word line are adjacent to each other via an insulating film. 
 
     
     
       6. The semiconductor memory device according to  claim 1 , further comprising:
 a fifth word line provided above the joint portion and adjacent to the joint portion; and 
 a sixth word line provided below the joint portion and adjacent to the joint portion, wherein 
 the first word line and the second word line are adjacent to each other via an insulating film, a distance between the first word line and the second word line is narrower than a distance between the fifth word line and the sixth word line. 
 
     
     
       7. The semiconductor memory device according to  claim 1 ,
 wherein, in a direction parallel to a surface of the substrate, a diameter of the joint portion is larger than a diameter of a contact portion between the first columnar portion and the joint portion and larger than a diameter of a contact portion between the second columnar portion and the joint portion. 
 
     
     
       8. The semiconductor memory device according to  claim 1 ,
 wherein the write operation includes a program operation performed after the precharge operation, 
 after the precharge operation is finished and before the program operation begins, the row decoder is configured to apply a fifth voltage to the select transistor, which turns off the select transistor. 
 
     
     
       9. The semiconductor memory device according to  claim 1 ,
 wherein the first pillar is a memory pillar. 
 
     
     
       10. A semiconductor memory device comprising:
 a first word line;   a second word line;   a first pillar including a first columnar portion, a second columnar portion, and a joint portion, the first columnar portion passing through the first word line, the joint portion being provided adjacent to the first columnar portion, the second columnar portion being provided adjacent to the joint portion, being provided above the first columnar portion, and passing through the second word line;   a select transistor provided for the first pillar;   a bit line connected to the second columnar portion; and   a row decoder configured to apply a voltage to the first and the second word lines; wherein   in a precharge operation performed during a write operation, the row decoder is configured to apply a first voltage to the first word line and apply a second voltage differing from the first voltage to the second word line.    
     
     
       11. The semiconductor memory device according to  claim 10 , further comprising a first dummy word line and a second dummy word line provided adjacent to the joint portion, wherein
 the first columnar portion passes through the first dummy word line,   the second columnar portion passes through the second dummy word line,   the first word line is farther from the joint portion than the first dummy word line is, and   the second word line is farther front the joint portion than the second dummy word line is.    
     
     
       12. The semiconductor memory device according to  claim 11 , further comprising:
 a first memory cell transistor provided between the first columnar portion and the first word line;   a second memory cell transistor provided between the second columnar portion and the second word line;   a first dummy transistor provided between the first columnar portion and the first dummy word line; and   a second dummy transistor provided between the second columnar portion and the second dummy word line.    
     
     
       13. The semiconductor memory device according to  claim 12 , wherein the first and the second dummy transistors are not used for data storage.  
     
     
       14. The semiconductor memory device according to  claim 10 , wherein, in a direction to which the first word line extends, a diameter of the first columnar portion where the first columnar portion and the joint portion are connected is larger than a diameter of the second columnar portion where the second columnar portion and the joint portion are connected.  
     
     
       15. The semiconductor memory device according to  claim 10 , wherein, after the precharge operation is finished, the row decoder is configured to apply a ground voltage to the second word line.  
     
     
       16. The semiconductor memory device according to  claim 10 , wherein the second voltage is higher than the first voltage.  
     
     
       17. The semiconductor memory device according to  claim 10 , wherein the first voltage is a ground voltage.  
     
     
       18. The semiconductor memory device according to  claim 12 , wherein, before performing the precharge operation, the row decoder is configured to apply a third voltage to the second word line, the first dummy word line, and the second dummy word line.  
     
     
       19. A semiconductor memory device comprising:
 a first word line;   a second word line;   a first pillar including a first columnar portion and a second columnar portion, the first columnar portion passing through the first word line, the second columnar portion passing through the second word line, being provided above the first columnar portion, and being connected to the first columnar portion;   a select transistor provided for the first pillar;   a bit line connected to the second columnar portion; and   a row decoder configured to apply a voltage to the first and the second word lines; wherein   in a precharge operation performed during a write operation, the row decoder is configured to apply a first voltage to the first word line and apply a second voltage differing from the first voltage to the second word line.    
     
     
       20. The semiconductor memory device according to  claim 19 , further comprising:
 a first dummy word line provided closer to the second columnar portion than the first word line is; and   a second dummy word line provided closer to the first columnar portion than the second word line is.    
     
     
       21. The semiconductor memory device according to  claim 19 , further comprising:
 a first memory cell transistor provided between the first columnar portion and the first word line;   a second memory cell transistor provided between the second columnar portion and the second word line;   a first dummy transistor provided between the first columnar portion and the first dummy word line; and   a second dummy transistor provided between the second columnar portion and the second dummy word line.    
     
     
       22. The semiconductor memory device according to  claim 21 , wherein the first and the second dummy transistors are not used for data storage.  
     
     
       23. The semiconductor memory device according to  claim 19 , wherein, in a direction to which the fast word line extends, a diameter of a top portion of the first columnar portion is larger than a diameter of a bottom portion of the second columnar portion.  
     
     
       24. The semiconductor memory device according to  claim 19 , wherein, after the precharge operation is finished, the row decoder is configured to apply a ground voltage to the second word line.  
     
     
       25. The semiconductor memory device according to  claim 19 , wherein the second voltage is higher than the first voltage.  
     
     
       26. The semiconductor memory device according to  claim 19 , wherein the first voltage is a ground voltage.  
     
     
       27. The semiconductor memory device according to  claim 20 , wherein, before performing the precharge operation, the row decoder is configured to apply a third voltage to the second word line, the first dummy word line, and the second dummy word line.  
     
     
       28. The semiconductor memory device according to  claim 20 , wherein the first dummy word line and the second dummy word line are adjacent to each other.