Semiconductor device and semiconductor device manufacturing method

Abstract

In the present invention, there is provided a semiconductor device including: element isolation regions formed in a state of being buried in a semiconductor substrate such that an element formation region of the semiconductor substrate is interposed between the element isolation regions; a gate electrode formed on the element formation region with an gate insulating film interposed between the gate electrode and the element formation region, the gate electrode being formed so as to cross the element formation region; and source-drain regions formed in the element formation region on both sides of the gate electrode, wherein a channel region made of the element formation region under the gate electrode is formed so as to project from the element isolation regions, and the source-drain regions are formed to a position deeper than surfaces of the element isolation regions.

What is claimed is: 
     
       1. A semiconductor device comprising:
 semiconductor substrate with an element formation region projecting from a base portion of said substrate and extending in a first direction along said base portion;   element isolation regions buried in said semiconductor substrate such that said element formation region of said semiconductor substrate is flanked by said element isolation regions, said element isolation regions having upper surfaces;   a gate electrode on said element formation region with a gate insulating film interposed between said gate electrode and said element formation region, said gate electrode crossing said element formation region in a second direction; and   source-drain regions formed in said element formation region on both sides of said gate electrode,   wherein,
 said element formation region includes a channel region under said gate electrode, 
 said source-drain regions are positioned within said element formation region so as to extend below said upper surfaces of said element isolation regions, 
 said element isolation regions include depressions in said upper surfaces which extend in said second direction and which flank said channel region, 
 said gate electrode extends into said depressions in said upper surfaces of said element isolation regions and has an upper surface positioned above bottom surfaces of said depressions, and 
 said channel region has an upper surface positioned above said bottom surfaces of said depressions. 
   
     
     
       2. The semiconductor device according to  claim 1 ,
 wherein surfaces of said source-drain regions are at one of a position equal in height to a surface of said semiconductor substrate and a position higher than the surface of said semiconductor substrate.   
     
     
       3. The semiconductor device according to  claim 1 , comprising a stress applying film which applies stress to said channel region. 
     
     
       4. The semiconductor device according to  claim 1 , comprising
 a stress applying insulating film covering said gate electrode which applies stress to said channel region.   
     
     
       5. The semiconductor device of  claim 1 , further comprising a silicide layer on said element formation region. 
     
     
       6. The semiconductor device of  claim 1 , wherein a difference between said channel region and said bottom surfaces of said depressions is from  3  nm to  30  nm, inclusive. 
     
     
       7. The semiconductor device of  claim 1 , wherein said element formation region includes SiGe regions in which said source and drain are located. 
     
     
       8. The semiconductor device of  claim 3 , wherein said stress applying layer is an SiN film. 
     
     
       9. The semiconductor device of  claim 4 , wherein said stress applying layer is an SiN film. 
     
     
       10. A semiconductor device comprising:
 a semiconductor substrate having:
 an element formation region that, in a perspective view of the semiconductor device, extends in a first direction and a second direction, wherein a first extension of the element formation region in the first direction is greater than a second extension of the element formation region in the second direction, 
 a silicon channel region of the element formation region, and 
 silicon germanium source-drain regions of the element formation region; 
   a gate electrode configured to extend, in the perspective view, along the first direction and the second direction, wherein a first extension of the gate electrode in the first direction is less than a second extension of the gate electrode in the second direction, so that:
 the element formation region crosses the gate electrode, 
 the gate electrode is on the element formation region, and 
 the silicon channel region is between the silicon germanium source-drain regions and under the gate electrode; 
   element isolation regions that, in the perspective view, are:
 buried in the semiconductor substrate, and 
 between the gate electrode and the semiconductor substrate; and 
   a gate insulating film that, in a vertical sectional view of the semiconductor device, is:
 between the gate electrode and the silicon channel region, and 
 between the gate electrode and the element isolation regions, 
   wherein:
 the first direction is orthogonal to the second direction, 
 the element formation region protrudes from a base portion of the semiconductor substrate so that the element formation region, in the vertical sectional view, is between the element isolation regions, 
 the silicon germanium source-drain regions are on both sides of the gate electrode and extend below upper surfaces of the element isolation regions, 
 depressions into the upper surfaces of the element isolation regions flank the silicon channel region, 
 the gate electrode extends into the depressions so that, in the vertical sectional view, an upper surface of the gate electrode is above bottom surfaces of the depressions, and 
 junction positions of the silicon germanium source-drain regions are deeper than surfaces of the element isolation regions. 
   
     
     
       11. The semiconductor device of  claim 10 , wherein the element isolation regions are formed of an insulating thin film. 
     
     
       12. The semiconductor device of  claim 10 , wherein the semiconductor substrate is silicon. 
     
     
       13. The semiconductor device of  claim 10 , wherein surfaces of the silicon germanium source-drain regions are at one of a position equal in height to a surface of the semiconductor substrate and a position higher than the surface of the semiconductor substrate. 
     
     
       14. The semiconductor device of  claim 10 , further comprising:
 a stress applying film that is configured to apply stress to the silicon channel region.   
     
     
       15. The semiconductor device of  claim 14 , wherein the stress applying film is an SiN film. 
     
     
       16. The semiconductor device of  claim 10 , further comprising:
 a stress applying insulating film covering the gate electrode in a manner that applies stress to the silicon channel region.   
     
     
       17. The semiconductor device of  claim 16 , wherein the stress applying insulating film is an SiN film. 
     
     
       18. The semiconductor device of  claim 10 , further comprising:
 a silicide layer on the element formation region.   
     
     
       19. The semiconductor device of  claim 10 , wherein a difference between the silicon channel region and the bottom surfaces of the depressions is from 3 nm to 30 nm, inclusive. 
     
     
       20. The semiconductor device of  claim 10 , wherein an upper surface of the silicon channel region, in the vertical sectional view, is above the bottom surfaces of the depressions.