Radiation-tolerant unit MOSFET hardened against single event effect and total ionization dose effect

Abstract

Provided is a radiation-tolerant 3D unit MOSFET having at least one selected from a dummy drain (DD), an N-well layer (NW), a deep N-well layer (DNW), and a P+ layer to minimize an influence by a total ionization dose effect and an influence by a single event effect.

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows: 
     
       1. A radiation-tolerant 3-dimensional unit metal-oxide field-effect transistor (3D unit MOSFET) to reduce an influence by a current pulse generated due to a single event effect and an influence by a total ionization dose effect, the radiation-tolerant 3D unit MOSFET comprising:
 a gate; 
 a source and a drain; 
 a dummy drain (DD) connected with the source and the drain to be positioned on a Fin structure of the radiation-tolerant 3D unit MOSFET and being able to apply a voltage to disperse the current pulse generated due to the influence by the single event effect; and 
 an N-well layer formed while being spaced apart from the source and the drain, the gate, and the DD by a specific distance, wherein the N-well layer is formed on a surface of a substrate to surround the Fin structure of the radiation-tolerant 3D unit MOSFET, 
 wherein at least one plane, lateral to the Fin structure, included in the gate has the shape of the surrounding plane according to the Fin structure of the radiation-tolerant 3D unit MOSFET. 
 
     
     
       2. The radiation-tolerant 3D unit MOSFET of  claim 1 , wherein the DD is positioned to be connected with a neutral region connected with at least one of the source and the drain. 
     
     
       3. The radiation-tolerant 3D unit MOSFET of  claim 2 , wherein the DD is connected with at least one lateral side surface of a left side and a right side of the source and the drain, and formed in a ‘T’ shape, a substantial ‘C’ shape, or the ‘I’ shape. 
     
     
       4. The radiation-tolerant 3D unit MOSFET of  claim 1 , wherein the DD applies a voltage to the source and the drain, disperses a current flowing through the source and the drain due to the single event effect, and reduces the influence exerted on a circuit region or a system connected with a MOSFET. 
     
     
       5. The radiation-tolerant 3D unit MOSFET of  claim 1 , further comprising:
 an N-well/metal-1 via to additionally apply a voltage to the N-well layer, wherein the N-well/metal-1 via is formed in the surface of the substrate to overlap with the N-well layer. 
 
     
     
       6. The radiation-tolerant 3D unit MOSFET of  claim 1 , further comprising:
 a deep N-well layer formed at a lower portion of the Fin structure of the radiation-tolerant 3D unit MOSFET. 
 
     
     
       7. The radiation-tolerant 3D unit MOSFET of  claim 6 , wherein the deep N-well layer is formed under the gate, the source, the drain, the DD, and the N-well layer positioned in the Fin structure of the radiation-tolerant 3D unit MOSFET and formed with a length to cover a horizontal length the N-well layer. 
     
     
       8. A radiation-tolerant 3-dimensional unit metal-oxide field-effect transistor (3D unit MOSFET) to reduce an influence by a current pulse generated due to a single event effect and an influence by a total ionization dose effect, the radiation-tolerant 3D unit MOSFET comprising:
 a gate; 
 a source and a drain; and 
 a P+ layer positioned on a lateral side surface of a field oxide film positioned at a contact point between the gate and a substrate to prevent a leakage current path from being formed due to the influence by the total ionization dose effect, 
 wherein the P+ layer is subsequently formed using a P-type doping on the lateral side surface of the field oxide film. 
 
     
     
       9. The radiation-tolerant 3D unit MOSFET of  claim 8 , wherein the P+ layer prevents the leakage current path from being formed from a fixed charge produced at a surface of the field oxide film due to the influence by the total ionization dose effect. 
     
     
       10. The radiation-tolerant 3D unit MOSFET of  claim 8 , further comprising:
 a DD (dummy drain) connected with the source and the drain to be positioned on a Fin structure of the radiation-tolerant 3-D unit MOSFET and being able to apply a voltage, 
 wherein at least one plane, lateral to the Fin structure, included in the gate has the shape of the surrounding plane according to the Fin structure of the radiation-tolerant 3D unit MOSFET. 
 
     
     
       11. The radiation-tolerant 3D unit MOSFET of  claim 10 , further comprising:
 an N-well layer formed while being spaced apart from the gate, the source and the drain, and the DD (dummy drain) by a specific distance; and 
 a deep N-well layer formed at a lower portion of the Fin structure of the radiation-tolerant 3D unit MOSFET, such that the current pulse generated due to the single event effect to flow to the source and the drain is dispersed or blocked, 
 wherein the N-well layer is formed on a surface of the substrate to surround the Fin structure of the radiation-tolerant 3D unit MOSFET. 
 
     
     
       12. A radiation-tolerant 3-dimensional unit metal-oxide field-effect transistor (3D unit MOSFET) to reduce an influence by a current pulse generated due to a single event effect and an influence by a total ionization dose effect, the radiation-tolerant 3D unit MOSFET comprising:
 a gate; 
 a source and a drain; 
 a P+ layer positioned on a lateral side surface of a field oxide film positioned at a contact point between the gate and a substrate to prevent a leakage current path from being formed due to the influence by the total ionization dose effect, wherein the P+ layer is subsequently formed using a P-type doping on the lateral side surface of the field oxide film; and 
 a deep N-well layer formed at a lower portion of the Fin structure of the radiation-tolerant 3D unit MOSFET. 
 
     
     
       13. The radiation-tolerant 3D unit MOSFET of  claim 12 , wherein the deep N-well layer blocks electron hole pairs, which are generated by the influence of the single event effect, from being collected. 
     
     
       14. A radiation-tolerant integrated circuit comprising a plurality of 3-dimensional unit metal oxide silicon field effect transistors (3D unit MOSFETs), the plurality of 3D unit MOSFETs comprising:
 a first 3D unit MOSFET comprising:
 a first fin structure comprising a first source and a first drain; 
 a first gate positioned between the first source and the first drain so that the first source, the first gate and the first drain are aligned in a row; and 
 a P+ layer positioned internally in the first fin structure under the first gate and on a lateral side surface of the first fin structure; and 
   a second 3D unit MOSFET comprising:
 a second fin structure comprising a second source and a second drain; and 
 a second gate positioned between the second source and the second drain so that the second source, the second gate and the second drain are aligned in a row; and 
 a dummy drain positioned at a side of the second drain that is not facing the second gate or at a side of the second source that is not facing the second gate. 
   
     
     
       15. The radiation-tolerant integrated circuit of  claim 14 , wherein the P+ layer reduces a leakage current path generated due to radiation, and wherein the dummy drain reduces an influence of a current pulse generated due to radiation. 
     
     
       16. The radiation-tolerant integrated circuit of  claim 14 , wherein the P+ layer comprises a plurality of separate P+ layers. 
     
     
       17. The radiation-tolerant integrated circuit of  claim 14 , wherein the P+ layer's position along the first fin structure's height corresponds to a lower end of the first gate along the first gate's height. 
     
     
       18. The radiation-tolerant integrated circuit of  claim 14 , further comprising a silicon neutral region positioned between the dummy drain and the second drain or between the dummy drain and the second source. 
     
     
       19. The radiation-tolerant integrated circuit of  claim 18 , wherein the second gate, the second source, the second drain and the dummy drain are aligned in a row. 
     
     
       20. The radiation-tolerant integrated circuit of  claim 14 , wherein the first 3D unit MOSFET further comprises an N-type dummy drain positioned at a side of the first drain that is not facing the first gate or at a side of the first source that is not facing the first gate, wherein the N-type dummy drain reduces an influence of a current pulse generated due to radiation. 
     
     
       21. The radiation-tolerant integrated circuit of  claim 20 , further comprising a silicon neutral region positioned between the N-type dummy drain and the first drain or between the N-type dummy drain and the first source. 
     
     
       22. The radiation-tolerant integrated circuit of  claim 21 , wherein the first gate, the first source, the first drain and the N-type dummy drain are aligned in a row. 
     
     
       23. The radiation-tolerant integrated circuit of  claim 22 , further comprising an N+/metal-1 via positioned on a surface of the N-type dummy drain. 
     
     
       24. The radiation-tolerant integrated circuit of  claim 14 , wherein the second 3D unit MOSFET is a P-channel MOSFET (PMOS), and wherein the dummy drain is doped to be P-type. 
     
     
       25. The radiation-tolerant integrated circuit of  claim 24 , wherein the first 3D unit MOSFET further comprises a deep N-well layer positioned under the first source, the first gate, the first drain, and the P+ layer, or wherein the second 3D unit MOSFET further comprises a deep P-well layer positioned under the second source, the second gate, the second drain, and the dummy drain. 
     
     
       26. The radiation-tolerant integrated circuit of  claim 24 , wherein the first 3D unit MOSFET further comprises an N-well layer positioned in a row with the first source, the first gate and the first drain, or wherein the second 3D unit MOSFET further comprises a P-well layer that is positioned in a row with the second source, the second gate, the second drain and the dummy drain. 
     
     
       27. The radiation-tolerant integrated circuit of  claim 24 , wherein the second 3D unit MOSFET further comprises a P+/metal-1 via positioned on a surface of the dummy drain. 
     
     
       28. A radiation-tolerant integrated circuit comprising a plurality of 3-dimensional unit metal oxide silicon field effect transistors (3D unit MOSFETs), the plurality of 3D unit MOSFETs comprising:
 a first 3D unit MOSFET comprising:
 a first source; 
 a first gate; 
 a first drain, wherein the first gate is positioned between the first source and the first drain so that the first source, the first gate and the first drain are aligned in a row; 
 a first body (330, 411), wherein the first body is under the first source, the first gate and the first drain; and 
 a P+ layer positioned internally in the first body under the first gate and on a lateral side surface of the first body. 
   
     
     
       29. The radiation-tolerant integrated circuit of  claim 28 , wherein the plurality of 3D unit MOSFETs further comprising:
 a second 3D unit MOSFET comprising:
 a second source; 
   a second gate:
 a second drain, wherein the second gate is positioned between the second source and the drain so that the second source, the second gate and the second drain are aligned in a row; 
 a dummy drain positioned at a side of the second drain that is not facing the second gate or at a side of the second source that is not facing the second gate; and 
 a silicon neutral layer positioned between the dummy drain and the second drain or between the dummy drain and the second source. 
   
     
     
       30. The radiation-tolerant integrated circuit of  claim 29 , wherein the first 3D unit MOSFET and the second 3D unit MOSFET are each a gate-all-around (GAA) MOSFET. 
     
     
       31. The radiation-tolerant integrated circuit of  claim 29 , wherein the P+ layer reduces a leakage current path generated due to radiation, and wherein the dummy drain reduces an influence of a current pulse generated due to radiation.