P
USRE50686EActiveUtilityPatentIndex 62

Electronic device

Assignee: LG DISPLAY CO LTDPriority: Dec 25, 2019Filed: May 2, 2024Granted: Dec 2, 2025
Est. expiryDec 25, 2039(~13.5 yrs left)· nominal 20-yr term from priority
Inventors:CHEN HSIEN-TE
H10H 20/032H10H 20/034H10W 90/724H10W 72/07336H10W 72/07255H10W 72/2524H10W 90/00H10W 72/00H10W 72/20H10H 20/0364H10H 20/857Y02E10/50Y02P70/50H01L 2924/01322H01L 2924/01079H01L 2924/01049H01L 2924/01028H01L 2224/83805H01L 2224/16502H01L 2224/16227H01L 25/0753H01L 24/16
62
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Cited by
18
References
21
Claims

Abstract

An electronic device comprises a target substrate, a micro semiconductor structure array, a conductor array, and a connection layer. The micro semiconductor structure array is disposed on the target substrate. The conductor array corresponds to the micro semiconductor structure array, and electrically connects the micro semiconductor structure array to a pattern circuit of the target substrate. The conductors of the conductor array are independent from one another. Each conductor is an integrated member formed by eutectic bonding a conductive pad of the target substrate and a conductive electrode of the corresponding one of the micro semiconductor structures of the micro semiconductor structure array. The connection layer connects the micro semiconductor structures to the target substrate. The connection layer excludes a conductive material. The connection layer contacts and surrounds the conductors, so that the connection layer and the conductors together form a one-layer structure.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An electronic device, comprising:
 a target substrate;   a micro semiconductor structure array comprising a plurality of micro semiconductor structures arranged in an array disposed on the target substrate;   a conductor array comprising a plurality of conductors arranged in an array, wherein the conductors are disposed corresponding to the micro semiconductor structures and electrically connecting the micro semiconductor structures to the target substrate, the conductors are independent and individual to one another, each of at least one of the plurality of conductors corresponding to a micro semiconductor structure is an integrated member formed by eutectic bonding a conductive pad of the target substrate and a conductive electrode of a corresponding one of the plurality of micro semiconductor structures, and each of the at least one of the plurality of conductors comprises a first end connecting to the corresponding micro semiconductor structure, a second end connecting to the target substrate, and a peripheral portion connecting to the first end and the second end; and   a connection layer connecting the plurality of micro semiconductor structures to the target substrate, wherein the connection layer is nonconductive, and the connection layer contacts and surrounds the peripheral portion of each of the plurality of conductors, and the connection layer and the conductors together form a one-layer structure,   wherein the connection layer comprises a polymer material, the polymer material is defined with a viscosity-temperature variation characteristic, the polymer material has a first viscosity at a first temperature, a second viscosity at a second temperature, a third viscosity at a third temperature, a fourth viscosity at a fourth temperature, and a fifth viscosity at a fifth temperature, the first temperature to the fifth temperature are increased sequentially, the first temperature is a room temperature, the fifth temperature is a glass transition temperature of the polymer material, the third viscosity and the fifth viscosity are threshold values, the third viscosity is a minimum threshold value, the fifth viscosity is a maximum threshold value, the second viscosity is close to the third viscosity, the conductive pad comprises a first metal, the conductive electrode comprises a second metal, the first metal and the second metal have a eutectic temperature, the eutectic temperature is between the third temperature and the fourth temperature, the fourth temperature is the temperature of starting solidification of the polymer material.   
     
     
         2 . The electronic device of  claim 1 , wherein each of the plurality of conductors is formed by a eutectic bonding of an In—Au alloy system. 
     
     
         3 . The electronic device of  claim 1 , wherein each of the plurality of conductors is formed by a eutectic bonding of an In—Ni alloy system. 
     
     
         4 . The electronic device of  claim 1 , wherein a polymer material of the connection layer comprises an epoxy material, or an acrylic material. 
     
     
         5 . The electronic device of  claim 1 , wherein the polymer material of the connection layer has a solidification temperature of 170-220° C. 
     
     
         6 . The electronic device of  claim 1 , wherein the glass transition temperature of the polymer material is greater than 240° C. 
     
     
       7. The electronic device of  claim 1 , wherein the conductive pad and the conductive electrode are eutectic bonded to each other while applying a pressure to the plurality of micro semiconductor structures.  
     
     
       8. The electronic device of  claim 1 , wherein a temperature of the eutectic bonding is 160° C.  
     
     
       9. The electronic device of  claim 1 , wherein a material of the target substrate includes polymers, plastics, resins, polyimide, polyethylene naphthalate, polyethylene terephthalate, metal, foil, glass, quartz, glass fibers, flexible glass, a semiconductor, sapphire, a metal-glass fiber composite board, or a metal-ceramic composite board.  
     
     
       10. The electronic device of  claim 1 , wherein one unit of the conductive pad comprises a pair of conductive pads, and at least one of the micro semiconductor structures is a dual-electrode structure.  
     
     
       11. The electronic device of  claim 1 , wherein a dimension of the plurality of micro semiconductor structures is 25 μm or less.  
     
     
       12. The electronic device of  claim 1 , further comprising:
 a pattern circuit disposed on the target substrate, wherein the conductive pad is disposed on the pattern circuit.    
     
     
       13. The electronic device of  claim 1 , wherein the second temperature is lower than the third temperature by 10° C.  
     
     
       14. The electronic device of  claim 1 , wherein the fourth temperature is relatively higher than the third temperature by 90-100° C.  
     
     
       15. The electronic device of  claim 1 , wherein the fourth temperature is relatively higher than the eutectic temperature by 10-40° C.  
     
     
       16. The electronic device of  claim 1 , wherein the first metal and the second metal are indium and gold, respectively, or vice versa.  
     
     
       17. The electronic device of  claim 1 , wherein a ratio of the indium to the gold is 2:1.  
     
     
       18. The electronic device of  claim 1 , wherein the first metal and the second metal are indium and nickel, respectively, or vice versa.  
     
     
       19. The electronic device of  claim 1 , wherein the connection layer is formed by solidifying or curing the polymer material to reach stable bonds between polymer molecules of the polymer material.  
     
     
       20. The electrode device of  claim 19 , wherein a dimension of a pressing device configured to apply pressure to the plurality of micro semiconductor structures is smaller than that of the connection layer.  
     
     
       21. The electrode device of  claim 1 , wherein the plurality of micro semiconductor structures include at least one of a transistor, a photovoltaic device, a solar cell, a diode, a light-emitting diode, a laser diode, a p-n junction diode, a photodiode, an integrated circuit, and a sensor.

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