Switched capacitor regulators with flying-inverter-controlled power switches

Abstract

A switching capacitor regulator, comprising: a switching capacitor configured to switch between a first state and a second state, wherein, in the first state, a first node of the switching capacitor is coupled to a second terminal, and a second node of the switching capacitor is coupled to a fixed voltage level, and wherein, in the second state, the first node is coupled to a first terminal, and the second node is coupled to the second terminal; a power switch configured to couple the second node to the second terminal when the switching capacitor is in the second state; and a flying inverter configured to control the power switch, wherein the flying inverter has a positive power terminal and a negative power terminal, wherein the positive power terminal is coupled to the first node, and wherein the negative power terminal is coupled to the second node.

What is claimed is: 
     
         1 . A switching capacitor regulator, comprising:
 a first terminal;   a second terminal;   a switching capacitor configured to switch between a first state and a second state, wherein, in the first state, a first node of the switching capacitor is coupled to the second terminal, and a second node of the switching capacitor is coupled to a fixed voltage level, and wherein, in the second state, the first node of the switching capacitor is coupled to the first terminal, and the second node of the switching capacitor is coupled to the second terminal;   a first power switch configured to couple the second node of the switching capacitor to the second terminal when the switching capacitor is in the second state, wherein the first power switch is a negative channel metal-oxide semiconductor (NMOS) power switch;   a second power switch configured to couple the first node of the switching capacitor to the second terminal when the switching capacitor is in the first state, wherein the second power switch is controlled by a signal that switches between a first pair of voltage levels, and wherein the second power switch is a negative channel metal-oxide semiconductor (NMOS) power switch; and   a flyingan inverter configuredhaving an input, an output, a positive power terminal, and a negative power terminal, wherein the output of the inverter is coupled to a control input of the first power switch, wherein the flying inverter has a positive power terminal and a negative power terminal, wherein the positive power terminal is connected to the first node of the switching capacitor so as to always has have the same voltage as the first node of the switching capacitor, wherein the negative power terminal is connected to the second node of the switching capacitor so as to always has have the same voltage as the second node of the switching capacitor, and wherein the output of the flying inverter controls the first power switch using provides a signal that switches between a second pair of voltage levels that is different from the first pair of voltage levels.   
     
     
         2 . The switching capacitor regulator of  claim 1 , wherein the first terminal is configured as an input terminal, the second terminal is configured as an output terminal, and an output voltage produced at the output terminal is smaller than an input voltage received at the input terminal. 
     
     
         3 . The switching capacitor regulator of  claim 1 , wherein the first terminal is configured as an output terminal, the second terminal is configured as an input terminal, and an output voltage produced at the output terminal is larger than an input voltage received at the input terminal. 
     
     
         4 . The switching capacitor regulator of  claim 1 , wherein the switching capacitor regulator can be configured to operate in each of (i) a step-up mode wherein a voltage produced by the switching capacitor regulator is larger than a voltage received by the switching capacitor regulator and (ii) a step-down mode wherein a voltage produced by the switching capacitor regulator is smaller than a voltage received by the switching capacitor regulator. 
     
     
         5 . The switching capacitor regulator of  claim 1 , wherein the first power switch is a field effect transistor having a gate, and wherein the output of the flying inverter is coupled to the gate. 
     
     
         6 . The switching capacitor regulator of  claim 1 , wherein the switching capacitor regulator is configured to operate in a time-interleaved manner with a second switching capacitor regulator over a time period. 
     
     
         7 . The switching capacitor regulator of  claim 1 , wherein the second terminal is coupled to a battery. 
     
     
       8. A regulator, comprising:
 a first terminal;   a second terminal;   a capacitor configured to switch between a first state and a second state, wherein:
 in the first state, a first node of the capacitor is coupled to the second terminal, and a second node of the capacitor is coupled to a fixed voltage level; and 
 in the second state, the first node of the capacitor is coupled to the first terminal, and the second node of the capacitor is coupled to the second terminal; 
   a first power switch configured to couple the second node of the capacitor to the second terminal when the capacitor is in the second state, wherein the first power switch is a negative channel metal-oxide semiconductor (NMOS) power switch;   a second power switch configured to couple the first node of the capacitor to the second terminal when the capacitor is in the first state, wherein the second power switch is controlled by a signal that switches between a first pair of voltage levels, and wherein the second power switch is a negative channel metal-oxide semiconductor (NMOS) power switch; and   one of: at least one buffer; and at least one inverter, having an output coupled to a control input of the first power switch, having a positive power terminal that is coupled to the first node of the capacitor so as to always have the same voltage as the first node of the capacitor, having a negative power terminal that is coupled to the second node of the capacitor so as to always have the same voltage as the second node of the capacitor, and wherein the output provides a signal that switches between a second pair of voltage levels that is different from the first pair of voltage levels.   
     
     
       9. The regulator of  claim 8 , wherein the first terminal is configured as an input terminal, the second terminal is configured as an output terminal, and an output voltage produced at the output terminal is smaller than an input voltage received at the input terminal. 
     
     
       10. The regulator of  claim 8 , wherein the first terminal is configured as an output terminal, the second terminal is configured as an input terminal, and an output voltage produced at the output terminal is larger than an input voltage received at the input terminal. 
     
     
       11. The regulator of  claim 8 , wherein the regulator can be configured to operate in each of (i) a step-up mode wherein a voltage produced by the regulator is larger than a voltage received by the regulator and (ii) a step-down mode wherein a voltage produced by the regulator is smaller than a voltage received by the regulator. 
     
     
       12. The regulator of  claim 8 , wherein the first power switch is a field effect transistor having a gate, and wherein the output of the one of: at least one buffer; and at least one inverter is coupled to the gate. 
     
     
       13. The regulator of  claim 8 , wherein the regulator is configured to operate in a time-interleaved manner with a second regulator over a time period. 
     
     
       14. The regulator of  claim 8 , wherein the second terminal is coupled to a battery. 
     
     
       15. The regulator of  claim 8 , wherein the one of: at least one buffer; and at least one inverter is at least one buffer. 
     
     
       16. The regulator of  claim 8 , wherein the one of: at least one buffer; and at least one inverter is a chain of buffers. 
     
     
       17. The regulator of  claim 8 , wherein the one of: at least one buffer; and at least one inverter is at least one inverter. 
     
     
       18. The regulator of  claim 8 , wherein the one of: at least one buffer; and at least one inverter is a chain of inverters. 
     
     
       19. The regulator of  claim 8 , wherein the fixed voltage level is ground. 
     
     
       20. A circuit, having a first state and a second state, that is configured to be connected to a capacitor having a first node and a second node, comprising:
 a first terminal, wherein the first terminal is coupled to the first node when the circuit is in the second state;   a second terminal, wherein the second terminal is coupled to: the first node when the circuit is in the first state; and the second node when the circuit is in the second state;   a first power switch configured to couple the second node of the capacitor to the second terminal when the capacitor is in the second state, wherein the first power switch is a negative channel metal-oxide semiconductor (NMOS) power switch;   a second power switch configured to couple the first node of the capacitor to the second terminal when the capacitor is in the first state, wherein the second power switch is controlled by a signal that switches between a first pair of voltage levels, and wherein the second power switch is a negative channel metal-oxide semiconductor (NMOS) power switch; and   one of: at least one buffer; and at least one inverter, having an output coupled to a control input of the first power switch, having a positive power terminal that is coupled to the first node of the capacitor so as to always have the same voltage as the first node of the capacitor, having a negative power terminal that is coupled to the second node of the capacitor so as to always have the same voltage as the second node of the capacitor, and wherein the output provides a signal that switches between a second pair of voltage levels that is different from the first pair of voltage levels.   
     
     
       21. The circuit of  claim 20 , further comprising a fixed voltage level node that is coupled to the second node of the capacitor when the circuit is in the first state.