Error correction code circuits, semiconductor memory devices and memory systems

Abstract

An error correction code (ECC) circuit of a semiconductor memory device includes a syndrome generation circuit and a correction circuit. The syndrome generation circuit generates syndrome based on a message and first parity bits in a codeword read from a memory cell array by using one of a first parity check matrix and a second parity check matrix, in response to a decoding mode signal. The correction circuit receives the codeword, corrects at least a portion of (t1+t2) error bits in the codeword based on the syndrome and outputs a corrected message. Here, t1 and t2 are natural numbers, respectively.

What is claimed is: 
     
         1 . An error correction code (ECC) circuit of a semiconductor memory device, the ECC circuit comprising:
 a syndrome generation circuit configured to generate a syndrome based on a message and first parity bits in a codeword read from a memory cell array by using one of a first parity check matrix and a second parity check matrix, in response to a decoding mode signal, the message including system check bits;   an ECC encoder configured to generate the first parity bits based on the message;   a memory storing the first parity check matrix and the second parity check matrix, the first parity check matrix including the second parity check matrix and a third parity check matrix, the second parity check matrix being a system parity check matrix; and   a correction circuit configured to
 receive the codeword, 
 correct at least a portion of (t1+t2) error bits in the codeword, based on the syndrome, wherein t1 and t2 are natural numbers, and 
 output a corrected message. 
   
     
     
         2 . The ECC circuit of  claim 1 , wherein the syndrome generation circuit includes
 a switch circuit configured to
 receive the first parity check matrix and the second parity check matrix, and 
 select one of the first parity check matrix and the second parity check matrix in response to the decoding mode signal, and 
   a syndrome generator, connected to the switch circuit, configured to generate the syndrome based on the codeword by using the selected parity check matrix.   
     
     
         3 . The ECC circuit of  claim 2 , wherein
 the switch circuit is further configured to select the first parity check matrix if the decoding mode signal designates a first decoding mode, and   the syndrome generator is further configured to generate the syndrome based on the codeword by using the first parity check matrix, if the decoding mode signal designates the first decoding mode.   
     
     
         4 . The ECC circuit of  claim 3 , wherein
 the correction circuit is further configured to correct (t1+t2) error bits in the codeword based on the syndrome.   
     
     
         5 . The ECC circuit of  claim 2 , wherein
 the switch circuit is further configured to select the second parity check matrix if the decoding mode signal designates a second decoding mode; and   the syndrome generator is further configured to generate the syndrome based on the codeword by using the second parity check matrix, if the decoding mode signal designates the second decoding mode.   
     
     
         6 . The ECC circuit of  claim 5 , wherein
 the correction circuit is configured to correct t2 error bits in the codeword based on the syndrome.   
     
     
         7 . The ECC circuit of  claim 1 , wherein the correction circuit includes:
 an error locator polynomial calculator configured to calculate coefficients of an error locator polynomial based on the syndrome;   an error location calculator configured to generate an error location signal indicating a location of at least one error bit in the codeword, based on the error locator polynomial having the calculated coefficients; and   a data corrector configured to
 correct the at least one error bit in the codeword based on the error location signal, and 
 output the corrected message. 
   
     
     
         8 . The ECC circuit of  claim 1 , further comprising:
 a mode selector configured to generate the decoding mode signal.   
     
     
         9 . The ECC circuit of  claim 1 , further comprising:
 a memory configured to store the first parity check matrix and the second parity check matrix, wherein
 the first parity check matrix includes the second parity check matrix and a system parity check matrix, and   a memory controller is configured to
 generate the system parity check matrix, 
 transmit the message to the semiconductor memory device, and 
 use the system parity check matrix in ECC decoding. 
     
     
     
         10 . A semiconductor memory device, comprising:
 a memory cell array including a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines;   an error correction code (ECC) circuit configured to
 generate a codeword by performing ECC encoding on a message received from a memory controller, the message including system parity bits encoded by the memory controller based on a first generation matrix, and the codeword being generated based on a second generation matrix, 
 generate a syndrome based on the message and first parity bits in a read codeword from the memory cell array, 
 correct at least a portion of (t1+t2) error bits in the read codeword based on the syndrome, wherein t1 and t2 are natural numbers, and 
 output a corrected message; 
 a memory storing the second generation matrix, a first parity check matrix, and a second parity check matrix, the first parity check matrix including the second parity check matrix and a third parity check matrix, and the second parity check matrix being a system parity check matrix; and 
 a control logic circuit configured to control the ECC circuit based on a command and an address received from the memory controller. 
   
     
     
         11 . The semiconductor memory device of  claim 10 , wherein
 the error correction code circuit is configured to correct fewer than or equal to t2 error bits, and   the memory controller is configured to
 transmit the message to the semiconductor memory device, and 
 correct fewer than or equal to t1 error bits. 
   
     
     
         12 . The semiconductor memory device of  claim 10 , wherein the ECC circuit includes:
 an ECC encoder configured to perform the ECC encoding on the message; and   an ECC decoder, including:
 a syndrome generation circuit configured to generate the syndrome based on the message and the first parity bits by using one of a the first parity check matrix and a the second parity check matrix, in response to a decoding mode signal; and 
 a correction circuit configured to correct at least the portion of (t1+t2) error bits in the codeword based on the syndrome and configured to output the corrected message. 
   
     
     
         13 . The semiconductor memory device of  claim 12 , wherein the syndrome generation circuit includes:
 a switch circuit configured to
 receive the first parity check matrix and the second parity check matrix, and 
 select one of the first parity check matrix and the second parity check matrix in response to the decoding mode signal, and 
   a syndrome generator, connected to the switch circuit, configured to generate the syndrome based on the codeword by using the selected parity check matrix.   
     
     
         14 . The semiconductor memory device of  claim 13 , wherein
 the switch circuit is further configured to select the first parity check matrix if the decoding mode signal designates a first decoding mode,   the syndrome generator is further configured to generate the syndrome based on the codeword by using the first parity check matrix if the decoding mode signal designates the first decoding mode, and   the correction circuit is further configured to correct (t1+t2) error bits in the codeword based on the syndrome.   
     
     
         15 . The semiconductor memory device of  claim 13 , wherein
 the switch circuit is further configured to select the second parity check matrix if the decoding mode signal designates a second decoding mode,   the syndrome generator is further configured to generate the syndrome based on the codeword by using the second parity check matrix, if the decoding mode signal designates the second decoding mode, and   the correction circuit is further configured to correct t2 error bits in the codeword based on the syndrome.   
     
     
         16 . The semiconductor memory device of  claim 12 , wherein the ECC circuit further includes:
 a mode selector configured to generate the decoding mode signal based on a control signal;, and   a memory configured to store the second generation matrix, the first parity check matrix and the second parity check matrix, wherein   the first parity check matrix includes the second parity check matrix and a system parity check matrix, and   wherein the memory controller is configured to use the system parity check matrix in ECC decoding.   
     
     
         17 . The semiconductor memory device of  claim 12 , wherein
 each of the plurality of memory cells includes a dynamic memory cell,   the first parity check matrix represents a double error correction (DEC) code, and   the second parity check matrix represents a single error correction (SEC) code.   
     
     
         18 . The semiconductor memory device of  claim 10 , further comprising:
 at least one buffer die; and   a plurality of memory dies stacked on the at least one buffer die and conveying data through a plurality of through silicon via (TSV) lines, wherein
 at least one of the plurality of memory dies includes the memory cell array and the ECC circuit, 
 the ECC circuit generates transmission parity bits using transmission data to be sent to the at least one buffer die, and 
 the at least one buffer die includes a via ECC engine configured to correct a transmission error using the transmission parity bits in response to the transmission error being detected from the transmission data received through the plurality of TSV lines. 
   
     
     
         19 . A memory system comprising:
 a semiconductor memory device; and   a memory controller configured to control the semiconductor memory device, the memory controller including,   a system error correction code (ECC) engine circuit including a system ECC encoder configured to perform system ECC encoding on data bits using a first generation matrix to generate a message,   wherein the semiconductor memory device includes,
 a memory cell array including a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines, 
 an ECC circuit configured to,
 generate a codeword by performing ECC encoding on the message received from the memory controller based on a second generation matrix, 
 generate a syndrome based on the message and first parity bits in a read codeword from the memory cell array, 
 correct at least a portion of (t1+t2) error bits in the read codeword based on the syndrome, wherein t1 and t2 are natural numbers, and 
 output a corrected message, 
 the ECC circuit including a memory storing the second generation matrix, a first parity check matrix, and a second parity check matrix, the first parity check matrix including the second parity check matrix and a third parity check matrix, and the second parity check matrix being a system parity check matrix, and 
 
 a control logic circuit configured to control the ECC circuit based on a command and an address received from the memory controller. 
   
     
     
         20 . The memory system of  claim 19 , wherein the ECC circuit includes:
 an ECC encoder configured to perform the ECC encoding on the message, and   an ECC decoder including,
 a syndrome generation circuit configured to generate the syndrome based on the message and the first parity bits by using one of a the first parity check matrix and a the second parity check matrix, in response to a decoding mode signal, and 
 a correction circuit configured to,
 correct at least the portion of (t1+t2) error bits in the codeword based on the syndrome, and 
 output the corrected message, 
 
   wherein the system ECC engine circuit is configured to correct fewer than or equal to t1 error bits, and   the ECC circuit is configured to correct fewer than or equal to (t1+t2) error bits.   
     
     
       21. A storage device comprising:
 a controller including a first error correction code (ECC) circuit; and   a memory device including a plurality of dies that include a first die and a second die,   wherein the first die includes a second ECC circuit and the second die includes a third ECC circuit, the second ECC circuit being a cell core ECC circuit and the third ECC circuit being a via ECC circuit, the cell core ECC circuit including a first ECC logic and the via ECC circuit including a second ECC logic different from the first ECC logic,   the first ECC circuit is configured to generate a first message for first data received from an external host,   the first message is first ECC encoded data, and includes first parity bits,   the second ECC circuit is configured to generate second ECC encoded data based on the first message by generating second parity bits based on the first message,   the first die includes a memory cell array that stores the second ECC encoded data,   the second ECC circuit is configured to correct at least a portion of error bits in a codeword that includes the first ECC encoded data, and   the third ECC circuit is configured to generate third ECC encoded data based on a second message by generating third parity bits based on the second message, and   the first ECC circuit is configured to correct m error bits, and the second ECC circuit is configured to correct n error bits, m being a positive integer, n being a positive integer that is different from m.    
     
     
       22. The storage device of  claim 21 , wherein the first ECC circuit includes an ECC encoder and an ECC decoder.  
     
     
       23. The storage device of  claim 21 , wherein the first ECC circuit transmits the first ECC encoded data as the codeword to the plurality of dies.  
     
     
       24. The storage device of  claim 21 , wherein the second ECC circuit corrects at least two error bits in the codeword.  
     
     
       25. The storage device of  claim 21 , wherein the controller writes the first data in response to a request from the external host.  
     
     
       26. The storage device of  claim 21 , wherein the second ECC circuit transmits a corrected message to the first ECC circuit.  
     
     
       27. A storage device comprising:
 a controller including a first error correction code (ECC) circuit; and   a high bandwidth memory (HBM) including a plurality of dies that include a first die and a second die,   wherein the first die includes a second ECC circuit, and the second die includes a third ECC circuit, the second ECC circuit being a cell core ECC circuit and the third ECC circuit being a via ECC circuit, the cell core ECC circuit including a first ECC logic and the via ECC circuit including a second ECC logic different from the first ECC logic,   the first ECC circuit is configured to generate a first message for first data received from an external host,   the first message is first error correction/detection data, and includes system parity bits,   the second ECC circuit is configured to generate second error correction/detection data based on the first message by generating second parity bits based on the first message,   the first die includes a memory cell array that stores the second error correction/detection data,   the second ECC circuit is configured to correct at least a portion of error bits in a codeword that includes the first error correction/detection data,   the third ECC circuit is configured to generate third ECC encoded data based on a second message by generating third parity bits based on the second message, and   the first ECC circuit is configured to correct m error bits, and the second ECC circuit is configured to correct n error bits, m being a positive integer, n being a positive integer that is different from m.    
     
     
       28. The storage device of  claim 27 , wherein the first ECC circuit transmits the first error correction/detection data as the codeword to the plurality of dies.  
     
     
       29. The storage device of  claim 27 , wherein the second ECC circuit transmits a corrected message to the first ECC circuit.  
     
     
       30. The storage device of  claim 27 , wherein the plurality of dies include a buffer die.  
     
     
       31. The storage device of  claim 27 , wherein the first ECC circuit includes an ECC encoder and an ECC decoder.  
     
     
       32. The storage device of  claim 27 , wherein the HBM is a stacked memory.  
     
     
       33. The storage device of  claim 27 , wherein the third ECC circuit is configured to correct p error bits, p being a positive integer that is different from m.