Three-dimensional semiconductor memory devices including a first contact with a sidewall having a stepwise profile

Abstract

Disclosed is a three-dimensional semiconductor device including a stack structure on a substrate and including electrodes that are vertically stacked on top of each other on a first region of a substrate, a vertical structure penetrating the stack structure and including a first semiconductor pattern, a data storage layer between the first semiconductor pattern and at least one of the electrodes, a transistor on a second region of the substrate, and a first contact coupled to the transistor. The first contact includes a first portion and a second portion on the first portion. Each of the first portion and the second portions has a diameter that increases with an increasing vertical distance from the substrate. A diameter of an upper part of the first portion is greater than a diameter of a lower part of the second portion.

What is claimed is: 
     
         1 . A three-dimensional (3D) semiconductor memory device, comprising:
 a substrate;   a stack structure on the substrate, the stack structure including electrodes that are vertically stacked on top of each other on the substrate;   a channel structure penetrating the stack structure;   a peripheral transistor on the substrate, the peripheral transistor being adjacent to the stack structure;   a first etch stop layer on the peripheral transistor;   a second etch stop layer on the first etch stop layer; and   a first contact penetrating the first etch stop layer and the second etch stop layer to being be electrically connected to the peripheral transistor,   wherein a sidewall of the first contact has a stepwise profile.   
     
     
         2 . The 3D semiconductor memory device of  claim 1 , further comprising:
 a second contact electrically connected to at least one of the electrodes of the stack structure,   wherein a sidewall of the second contact has a continuous profile.   
     
     
         3 . The 3D semiconductor memory device of  claim 2 , wherein the first contact and the second contact include a same conductive material. 
     
     
         4 . The 3D semiconductor memory device of  claim 2 , wherein a maximum diameter of the first contact is greater than a maximum diameter of the second contact. 
     
     
         5 . The 3D semiconductor memory device of  claim 1 , wherein the first contact includes a first portion and a second portion on the first portion, and
 a diameter of an upper part of the first portion is greater than a diameter of a lower part of the second portion.   
     
     
         6 . The 3D semiconductor memory device of  claim 1 , further comprising a buffer layer between the first and second etch stop layers,
 wherein the buffer layer has a planarized top surface.   
     
     
         7 . The 3D semiconductor memory device of  claim 6 , wherein the second etch stop layer on the buffer layer has a planarized top surface. 
     
     
         8 . The 3D semiconductor memory device of  claim 1 , wherein the peripheral transistor includes a gate electrode and a source/drain region, and
 wherein a top surface of the first etch stop layer is at a higher level on the gate electrode of the peripheral transistor than on the source/drain region of the peripheral transistor.   
     
     
         9 . The 3D semiconductor memory device of  claim 1 , wherein the first etch stop layer and the second etch stop layer each independently include at least one of a silicon nitride layer, a silicon oxynitride layer, or a polysilicon layer. 
     
     
         10 . A three-dimensional (3D) semiconductor memory device, comprising:
 a substrate;   a stack structure on the substrate, the stack structure including electrodes that are vertically stacked on top of each other on the substrate;   a channel structure penetrating the stack structure;   a peripheral transistor on the substrate, the peripheral transistor being adjacent to the stack structure;   a buffer layer on the peripheral transistor, the buffer layer having a planarized top surface;   an etch stop layer on the planarized top surface of the buffer layer; and   a first contact penetrating the etch stop layer and the buffer layer to being be electrically connected to the peripheral transistor,   wherein a sidewall of the first contact has a stepwise profile.   
     
     
         11 . The 3D semiconductor memory device of  claim 10 , further comprising a second contact electrically connected to at least one of the electrodes of the stack structure,
 wherein a sidewall of the second contact has a continuous profile.   
     
     
         12 . The 3D semiconductor memory device of  claim 11 , wherein the first contact and the second contact include a same conductive material. 
     
     
         13 . The 3D semiconductor memory device of  claim 11 , wherein a maximum diameter of the first contact is greater than a maximum diameter of the second contact. 
     
     
         14 . The 3D semiconductor memory device of  claim 10 , wherein the first contact includes a first portion and a second portion on the first portion, and
 a diameter of an upper part of the first portion is greater than a diameter of a lower part of the second portion.   
     
     
         15 . A three-dimensional (3D) semiconductor memory device, comprising:
 a substrate;   a stack structure on the substrate, the stack structure including electrodes that are vertically stacked on top of each other on the substrate;   a channel structure penetrating the stack structure;   a peripheral transistor on the substrate, the peripheral transistor being adjacent to the stack structure;   an etch stop layer on the peripheral transistor;   a first contact penetrating the etch stop layer to being be electrically connected to the peripheral transistor; and   a second contact electrically connected to at least one of the electrodes of the stack structure,   wherein a sidewall of the first contact has a stepwise profile, and   wherein a sidewall of the second contact has a continuous profile.   
     
     
         16 . The 3D semiconductor memory device of  claim 15 , wherein the first contact includes a first portion and a second portion on the first portion, and
 a diameter of an upper part of the first portion is greater than a diameter of a lower part of the second portion.   
     
     
         17 . The 3D semiconductor memory device of  claim 15 , wherein a maximum diameter of the first contact is greater than a maximum diameter of the second contact. 
     
     
         18 . The 3D semiconductor memory device of  claim 15 , wherein the first contact and the second contact include a same conductive material. 
     
     
         19 . The 3D semiconductor memory device of  claim 15 , wherein the etch stop layer has a planarized top surface. 
     
     
         20 . The 3D semiconductor memory device of  claim 15 , wherein the peripheral transistor includes a gate electrode and a source/drain region, and
 wherein a top surface of the etch stop layer is at a higher level on the gate electrode of the peripheral transistor than on the source/drain region of the peripheral transistor.   
     
     
       21. A three-dimensional (3D) semiconductor memory device, comprising:
 a substrate;   a stack structure on the substrate, the stack structure including electrodes that are vertically stacked on top of each other on the substrate;   a channel structure penetrating the stack structure;   a peripheral transistor on the substrate, the peripheral transistor being adjacent to the stack structure;   a first etch stop layer on the peripheral transistor;   a second etch stop layer on the first etch stop layer; and   a first contact penetrating the first etch stop layer and the second etch stop layer to be electrically connected to the peripheral transistor,   wherein a sidewall of the first contact has a stepwise profile,   wherein the peripheral transistor includes a peripheral gate electrode and a source/drain region,   wherein the first etch stop layer is on a top surface and side surfaces of the peripheral gate electrode, and   wherein the second etch stop layer has a top surface, whose level is substantially the same regardless of whether the second etch stop layer is placed on either the peripheral gate electrode or the source/drain region.   
     
     
       22. The 3D semiconductor memory device of  claim 21 , further comprising a buffer layer between the first and second etch stop layers,
 wherein the buffer layer has a planarized top surface.   
     
     
       23. The 3D semiconductor memory device of  claim 22 , wherein the second etch stop layer is provided on the planarized top surface of the buffer layer, thereby having a flat profile. 
     
     
       24. The 3D semiconductor memory device of  claim 22 , wherein the planarized top surface of the buffer layer is closer to the top surface of the peripheral gate electrode than to a top surface of the substrate. 
     
     
       25. The 3D semiconductor memory device of  claim 21 , further comprising gate spacers on the side surfaces of the peripheral gate electrode,
 wherein the first etch stop layer covers the gate spacers.   
     
     
       26. The 3D semiconductor memory device of  claim 21 , further comprising:
 a second contact electrically connected to at least one of the electrodes of the stack structure,   wherein a sidewall of the second contact has a continuous profile.   
     
     
       27. The 3D semiconductor memory device of  claim 26 , wherein the first contact and the second contact include a same conductive material. 
     
     
       28. The 3D semiconductor memory device of  claim 26 , wherein a maximum diameter of the first contact is greater than a maximum diameter of the second contact. 
     
     
       29. The 3D semiconductor memory device of  claim 26 , wherein the first contact includes a first portion and a second portion on the first portion, and
 a diameter of an upper part of the first portion is greater than a diameter of a lower part of the second portion.   
     
     
       30. The 3D semiconductor memory device of  claim 21 , wherein the first etch stop layer and the second etch stop layer each independently include at least one of a silicon nitride layer, a silicon oxynitride layer, or a polysilicon layer. 
     
     
       31. A three-dimensional (3D) semiconductor memory device, comprising:
 a substrate;   a stack structure on the substrate, the stack structure including electrodes that are vertically stacked on top of each other on the substrate;   a channel structure penetrating the stack structure;   a peripheral transistor on the substrate, the peripheral transistor being adjacent to the stack structure;   a first etch stop layer on the peripheral transistor;   a second etch stop layer on the first etch stop layer; and   a first contact penetrating the first etch stop layer and the second etch stop layer to be electrically connected to the peripheral transistor,   wherein a sidewall of the first contact has a stepwise profile,   wherein the peripheral transistor includes a peripheral gate electrode and a source/drain region,   wherein the second etch stop layer has a top surface, whose level is substantially the same regardless of whether the second etch stop layer is placed on either the peripheral gate electrode or the source/drain region, and   wherein the second etch stop layer is positioned higher than a top surface of the peripheral gate electrode and lower than a top surface of the first contact.   
     
     
       32. The 3D semiconductor memory device of  claim 31 , further comprising a buffer layer between the first and second etch stop layers,
 wherein the buffer layer has a planarized top surface.   
     
     
       33. The 3D semiconductor memory device of  claim 32 , wherein the second etch stop layer is provided on the planarized top surface of the buffer layer, thereby having a flat profile. 
     
     
       34. The 3D semiconductor memory device of  claim 32 , wherein the planarized top surface of the buffer layer is closer to the top surface of the peripheral gate electrode than to a top surface of the substrate. 
     
     
       35. The 3D semiconductor memory device of  claim 31 , further comprising a gate spacer on a side surface of the peripheral gate electrode,
 wherein the first etch stop layer covers the gate spacer.   
     
     
       36. The 3D semiconductor memory device of  claim 31 , further comprising:
 a second contact electrically connected to at least one of the electrodes of the stack structure,   wherein a sidewall of the second contact has a continuous profile.   
     
     
       37. The 3D semiconductor memory device of  claim 36 , wherein the first contact and the second contact include a same conductive material. 
     
     
       38. The 3D semiconductor memory device of  claim 36 , wherein a maximum diameter of the first contact is greater than a maximum diameter of the second contact. 
     
     
       39. The 3D semiconductor memory device of  claim 36 , wherein the first contact includes a first portion and a second portion on the first portion, and
 a diameter of an upper part of the first portion is greater than a diameter of a lower part of the second portion.   
     
     
       40. The 3D semiconductor memory device of  claim 31 , wherein the first etch stop layer and the second etch stop layer each independently include at least one of a silicon nitride layer, a silicon oxynitride layer, or a polysilicon layer.