Semiconductor device for short-circuiting nodes connected to a word line control circuit and control method for the same

Abstract

According to one embodiment, a semiconductor device includes a first voltage generator, a second voltage generator, a first MOS transistor, and a controller. The first voltage generator outputs a first voltage to a first node. The second voltage generator outputs a second voltage to a second node. The first MOS transistor is capable of short-circuiting the first node and second node. The controller performs a control operation to short-circuit the first node and second node by turning on the first MOS transistor. The controller controls a period in which the first MOS transistor is kept in an on state based on time.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first voltage generator circuit which outputs a first voltage to a first node;   a second voltage generator circuit which outputs a second voltage to a second node;   a first MOS transistor capable of short-circuiting the first node and second node; and   a controller which performs a control operation to short-circuit the first node and second node by turning on the first MOS transistor, controlling a period in which the first MOS transistor is kept in an on state based on time.   
     
     
         2 . The device according to  claim 1 , wherein a first load is connected to the first node, and a second load larger than the first load is connected to the second node,
 when a potential of the first load reaches the second voltage in a case where the first voltage is higher than the second voltage at a read time, the controller turns off the first MOS transistor.   
     
     
         3 . The device according to  claim 1 , wherein a first load is connected to the first node, and a second load larger than the first load is connected to the second node,
 in a case where the second voltage is higher than the first voltage at a read time, the controller turns off the first MOS transistor before a potential of the second load reaches the first voltage.   
     
     
         4 . The device according to  claim 1 , wherein the first MOS transistor is one of an n-type intrinsic MOS transistor, depression-type MOS transistor, and enhancement-type MOS transistor. 
     
     
         5 . The device according to  claim 1 , wherein the controller
 senses a potential of the second node, and   transfers a voltage equal to the sum of the above potential and a threshold voltage of the first MOS transistor to the gate of the first MOS transistor.   
     
     
         6 . The device according to  claim 1 , further comprising:
 a third voltage generator circuit which outputs a third voltage to a third node; and   a second MOS transistor capable of short-circuiting the second node and the third node,   wherein the controller simultaneously performs on and off switching operations of the first MOS transistor and second MOS transistor.   
     
     
         7 . The device according to  claim 6 , wherein the controller
 senses a potential of one of the second node and the third node, and   transfers one of a first voltage equal to the sum of the above potential and a first threshold voltage of the first MOS transistor and a second voltage equal to the sum of the above potential and a second threshold voltage of the second MOS transistor to the gates of the first and second MOS transistors.   
     
     
         8 . The device according to  claim 1 , further comprising:
 a memory cell array including plural memory cells whose current paths are serially connected and each of which includes a charge storage layer and control gate; and   word lines connected to the control gates of the memory cells and each used as one of the first and second loads;   wherein the first and second voltage generator circuits transfer one of the first and second voltages to the word lines.   
     
     
         9 . A semiconductor device comprising:
 a memory cell array including i memory cells (i is an integral number larger than 2) capable of holding data each of which includes a charge storage layer and control gate and the i memory cells are serially connected along a current path; and   a voltage generator circuit which generates a first voltage and second voltage, transferring the first and second voltages to word lines connected to the control gates of the memory cells,   wherein the voltage generator circuit   transfers the first voltage to the word line connected to the control gate of the ith memory cell, and   transfers the second voltage to the word lines connected to the control gates of the (i+1)th and (i+2)th memory cells which are arranged on a drain side of the ith memory cell.   
     
     
         10 . The device according to  claim 9 , wherein the first voltage is a voltage corresponding to data held by the ith memory cell. 
     
     
         11 . The device according to  claim 9 , further comprising:
 a MOS transistor capable of short-circuiting a first node and second node; and   a controller which performs a control operation to turn on the MOS transistor to short-circuit the first node and second node,   wherein the voltage generator circuit includes   a first voltage generator circuit which generates the first voltage and outputs the first voltage to the first node, and   a second voltage generator circuit which generates the second voltage and outputs the second voltage to the second node, and   the controller controls a period in which the MOS transistor is maintained in an on state based on time.   
     
     
         12 . The device according to  claim 11 , wherein the controller
 senses a potential of the second node, and   transfers a voltage equal to the sum of the above   potential and a threshold voltage of the MOS transistor to the gate of the MOS transistor.   
     
     
         13 . The device according to  claim 9 , wherein the MOS transistor is one of an n-type intrinsic MOS transistor, depression-type MOS transistor, and enhancement-type MOS transistor. 
     
     
         14 . The device according to  claim 11 , wherein a word line used as a first load is connected to the first node, and a word line used as a second load larger than the first load is connected to the second node, and
 in a case where the second voltage is higher than the first voltage, the controller turns off the first MOS transistor before a potential of the second load reaches the first voltage.   
     
     
         15 . A control method of a semiconductor device comprising:
 causing a first voltage generator circuit to generate a first voltage and output the first voltage to a first node;   causing a second voltage generator circuit to generate a second voltage and output the second voltage to a second node;   causing a controller to set a first MOS transistor in an on state and short-circuit the first node and second node; and   causing the controller to control a period in which the first MOS transistor is maintained in the on state based on time.   
     
     
         16 . The method according to  claim 15 , further comprising:
 causing the first voltage generator circuit to transfer the first voltage to a first load via the first node;   causing the second voltage generator circuit to transfer the second voltage higher than the first voltage to a second load larger than the first load via the second node; and   causing the controller to turn off the first MOS transistor before a potential of the second load reaches the first voltage.   
     
     
         17 . The method according to  claim 15 , further comprising:
 causing the first voltage generator circuit to transfer the first voltage to a first load via the first node;   causing the second voltage generator circuit to transfer the second voltage to a second load larger than the first load via the second node; and   if the first voltage is higher than the second voltage at a read time, causing the controller to turn off the first MOS transistor at the timing of a potential of the first load reaching the second voltage.   
     
     
         18 . The method according to  claim 15 , further comprising:
 causing the controller to sense a potential of the second node; and   causing the controller to transfer a voltage equal to the sum of the above potential and a threshold voltage of the first MOS transistor to the gate of the first MOS transistor.   
     
     
         19 . The method according to  claim 15 , further comprising:
 causing a third voltage generator circuit to generate a third voltage and output the third voltage to a third node;   causing the controller to turn on the first and second MOS transistors and short-circuit the first to third nodes; and   causing the controller to simultaneously perform on and off switching operations of the first and second MOS transistors.   
     
     
         20 . The method according to  claim 16 , further comprising:
 transferring the first voltage to a control gate of an ith memory cell among plural memory cells whose current paths are serially connected via the first node at a data read time; and   transferring the second voltage to a control gate of an (i+1)th memory cell arranged on a drain side of the ith memory cell via the second node.   
     
     
       21. A semiconductor device comprising:
 a memory cell array including a plurality of memory cells connected in series and each memory cell configured to store data;   a plurality of word lines connected to gates of the memory cells, respectively;   a word line control circuit configured to control the word lines;   a first node connected to the word line control circuit;   a second node connected to the word line control circuit;   a third node connected to the word line control circuit;   a first MOS transistor having one end connected to the first node, another end connected to the second node and a gate, the first transistor configured to equalize a voltage level of the first node and a voltage level of the second node by being turned on and short-circuiting the first node and the second node;   a second transistor having one end connected to the second node, another end connected to the third node and a gate, the second transistor configured to equalize the voltage level of the second node and a voltage level of the third node by being turned on and short-circuiting the second node and the third node; and   a controller connected to the gate of the first transistor and the gate of the second transistor and configured to perform a control operation to short circuit the first node and the second node by turning on the first MOS transistor for a first period of time, controlling a period in which the first MOS transistor is kept in an on state based on time,   wherein
 the duration of the first period during which the first transistor is turned on to short-circuit the first node and the second node is changed, 
 the voltage level of the first node is transferred to at least a first one of the word lines, 
 the voltage level of the second node is transferred to at least a second one of the word lines, and 
 the voltage level of the third node is transferred to at least a third one of the word lines. 
   
     
     
       22. The device according to  claim 21 , wherein
 in the control operation, the second node and the third node are short circuited by turning on the second transistor for a second period of time, and   the duration of the second period during which the second transistor is turned on to short-circuit the second node and the third node is changed.   
     
     
       23. The device according to  claim 22 , wherein
 the controller controls the first period of time and the second period.   
     
     
       24. The device according to  claim 23 , further comprising:
 first voltage generator circuitry including a first charge pump, and configured to output the first voltage to the first node;   second voltage generator circuitry including a second charge pump, and configured to output the second voltage to the second node; and   third voltage generator circuitry including a third charge pump, and configured to output the third voltage to the third node, wherein
 the second voltage is higher than the first voltage, and 
 the first transistor is turned on during the first period in which at least one of first voltage generator circuit and the second voltage generator circuit controls the voltage level of the first node and the voltage level of the second node to have the same voltage, and the first transistor is turned off during a third period of time after the first period in which the second voltage generator circuit controls the voltage level of the second node to return to the second voltage. 
   
     
     
       25. The device according to  claim 24 , wherein
 the second transistor is turned on during the second period, and the second transistor is turned off during a fourth period of time after the second period in which the third voltage generator circuit controls the voltage level of the third node toward the third voltage.   
     
     
       26. The device according to  claim 23 , wherein
 the first transistor is one of an n-type intrinsic MOS transistor, a depression-type transistor, and an enhancement-type MOS transistor, and   the second transistor is one of an n-type intrinsic MOS transistor, a depression-type transistor, and an enhancement-type MOS transistor.   
     
     
       27. The device according to  claim 23 , wherein
 a voltage equal to a sum of the voltage level of the second node and a threshold voltage of the first transistor is applied to the gate of the first transistor.   
     
     
       28. The device according to  claim 23 , wherein
 a voltage applied to the gates of the first and second transistors is one of
 a voltage equal to a sum of the voltage level of one of the second node and the third node and a threshold voltage of the first transistor, and 
 a voltage equal to a sum of the voltage level of one of the second node and the third node and a threshold voltage of the second transistor. 
   
     
     
       29. The device according to  claim 23 , wherein
 a signal is applied to the gate of the first transistor and the gate of the second transistor.   
     
     
       30. The device according to  claim 23 , wherein
 the first transistor is one of an n-type depletion MOS transistor with high withstand voltage and an n-type enhancement MOS transistor with high withstand voltage, and   the second transistor is one of an n-type depletion MOS transistor with high withstand voltage and an n-type enhancement MOS transistor with high withstand voltage.   
     
     
       31. A method for controlling a semiconductor device, the semiconductor device including:
 a memory cell array including a plurality of memory cells connected in series and eac memory cell configured to store data;   a plurality of word lines connected to gates of the memory cells, respectively;   a word line control circuit configured to control the word lines;   a first node connected to the word line control circuit;   a second node connected to the word line control circuit;   a third node connected to the word line control circuit;   a first MOS transistor having one end connected to the first node, another end connected to the second node and a gate, the first transistor configured to equalize a voltage level of the first node and a voltage level of the second node by being turned on and short-circuiting the first node and the second node:   a second transistor having one end connected to the second node, another end connected to the third node and a gate. the second transistor configured to equalize the voltage level of the second node and a voltage level of the third node by being turned on and short-circuiting the second node and the third node,   the method comprising:
 causing a controller to supply a control signal to set the gate of the first MOS transistor and the gate of the second transistor to thereby perform a control operation to short circuit the first node and the second node by turning on the first transistor for a first period of time and short circuit the second node and the third node by turning on the second transistor for a second period of time, 
   wherein
 the duration of the first period during which the first transistor is turned on to short-circuit the first node and the second node is changed, 
 the voltage level of the first node is transferred to at least a first one of the word lines, 
 the voltage level of the second node is transferred to at least a second one of the word lines, and 
 the voltage level of the third node is transferred to at least a third one of the word lines.