Assignee
CAMACHO ZIGMUND R
SG·22 granted patents·2 pending applications·355 citations·filing 2006–2012
Top patents by PatentIndex Score
24 records- 0198US9177832B2Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnectCAMACHO ZIGMUND R·Filed 2011·Granted Nov 3, 2015·48 cites·28 claims
- 0298US8993376B2Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor dieCAMACHO ZIGMUND R·Filed 2011·Granted Mar 31, 2015·52 cites·23 claims
- 0398US8409922B2Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnectCAMACHO ZIGMUND R·Filed 2010·Granted Apr 2, 2013·58 cites·31 claims
- 0498US8076184B1Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor dieCAMACHO ZIGMUND R·Filed 2010·Granted Dec 13, 2011·43 cites·12 claims
- 0597US9006031B2Semiconductor device and method of forming EWLB package with standoff conductive layer over encapsulant bumpsCAMACHO ZIGMUND R·Filed 2011·Granted Apr 14, 2015·40 cites·24 claims
- 0696US8241956B2Semiconductor device and method of forming wafer level multi-row etched lead packageCAMACHO ZIGMUND R·Filed 2010·Granted Aug 14, 2012·25 cites·20 claims
- 0794US8884418B2Semiconductor device and method of forming PIP with inner known good die interconnected with conductive bumpsCAMACHO ZIGMUND R·Filed 2012·Granted Nov 11, 2014·15 cites·25 claims
- 0892US8389333B2Semiconductor device and method of forming EWLB package containing stacked semiconductor die electrically connected through conductive vias formed in encapsulant around dieCAMACHO ZIGMUND R·Filed 2011·Granted Mar 5, 2013·12 cites·25 claims
- 0987US9922955B2Semiconductor device and method of forming package-on-package structure electrically interconnected through TSV in WLCSPCAMACHO ZIGMUND R·Filed 2010·Granted Mar 20, 2018·9 cites·17 claims
- 1086US8105915B2Semiconductor device and method of forming vertical interconnect structure between non-linear portions of conductive layersCAMACHO ZIGMUND R·Filed 2009·Granted Jan 31, 2012·12 cites·25 claims
- 1182US8241954B2Wafer level die integration and methodCAMACHO ZIGMUND R·Filed 2007·Granted Aug 14, 2012·9 cites·24 claims
- 1281US8283209B2Semiconductor device and method of forming PiP with inner known good die interconnected with conductive bumpsCAMACHO ZIGMUND R·Filed 2009·Granted Oct 9, 2012·7 cites·25 claims
- 1379US9142514B2Semiconductor device and method of forming wafer level die integrationCAMACHO ZIGMUND R·Filed 2012·Granted Sep 22, 2015·4 cites·20 claims
- 1476US8502376B2Wirebondless wafer level package with plated bumps and interconnectsCAMACHO ZIGMUND R·Filed 2011·Granted Aug 6, 2013·3 cites·28 claims
- 1575US8722457B2System and apparatus for wafer level integration of componentsCAMACHO ZIGMUND R·Filed 2007·Granted May 13, 2014·6 cites·25 claims
- 1675US8586422B2Optical semiconductor device having pre-molded leadframe with window and method thereforCAMACHO ZIGMUND R·Filed 2012·Granted Nov 19, 2013·3 cites·19 claims
- 1772US8546189B2Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnectionCAMACHO ZIGMUND R·Filed 2009·Granted Oct 1, 2013·4 cites·22 claims
- 1870US8138027B2Optical semiconductor device having pre-molded leadframe with window and method thereforCAMACHO ZIGMUND R·Filed 2008·Granted Mar 20, 2012·3 cites·31 claims
- 1965US9129971B2Semiconductor device with bump interconnectionCAMACHO ZIGMUND R·Filed 2011·Granted Sep 8, 2015·1 cites·30 claims
- 2064US8866248B2Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the deviceCAMACHO ZIGMUND R·Filed 2010·Granted Oct 21, 2014·1 cites·28 claims
- 2154US9525080B2Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the deviceCAMACHO ZIGMUND R·Filed 2012·Granted Dec 20, 2016·0 cites·25 claims
- 2251US8890328B2Semiconductor device and method of forming vertical interconnect structure between non-linear portions of conductive layersCAMACHO ZIGMUND R·Filed 2011·Granted Nov 18, 2014·0 cites·28 claims
- 2349US2012273927A1Semiconductor Device and Method of Forming Wafer Level Multi-Row Etched Lead PackageCAMACHO ZIGMUND R·Filed 2012·Application pending·0 cites
- 2442US2007170558A1Stacked integrated circuit package systemCAMACHO ZIGMUND R·Filed 2006·Application pending·0 cites
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