Assignee
INST THE DEV OF EMERGING ARCHI
US·37 granted patents·2,120 citations·filing 1995–2001
Top patents by PatentIndex Score
37 records- 0190US5815720AUse of dynamic translation to collect and exploit run-time information in an optimizing compilation systemINST THE DEV OF EMERGING ARCHI·Filed 1996·Granted Sep 29, 1998·172 cites·19 claims
- 0289US5903750ADynamic branch prediction for branch instructions with multiple targetsINST THE DEV OF EMERGING ARCHI·Filed 1996·Granted May 11, 1999·161 cites·19 claims
- 0387US6088780APage table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual addressINST THE DEV OF EMERGING ARCHI·Filed 1997·Granted Jul 11, 2000·141 cites·35 claims
- 0486US6151669AMethods and apparatus for efficient control of floating-point status registerINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Nov 21, 2000·122 cites·31 claims
- 0583US6631460B1Advanced load address table entry invalidation based on register address wraparoundINST THE DEV OF EMERGING ARCHI·Filed 2000·Granted Oct 7, 2003·47 cites·32 claims
- 0683US6393544B1Method and apparatus for calculating a page table index from a virtual addressINST THE DEV OF EMERGING ARCHI·Filed 1999·Granted May 21, 2002·113 cites·20 claims
- 0783US5742804AInstruction prefetch mechanism utilizing a branch predict instructionINST THE DEV OF EMERGING ARCHI·Filed 1996·Granted Apr 21, 1998·109 cites·12 claims
- 0882US5922065AProcessor utilizing a template field for encoding instruction sequences in a wide-word formatINST THE DEV OF EMERGING ARCHI·Filed 1997·Granted Jul 13, 1999·120 cites·31 claims
- 0978US5652859AMethod and apparatus for handling snoops in multiprocessor caches having internal buffer queuesINST THE DEV OF EMERGING ARCHI·Filed 1995·Granted Jul 29, 1997·84 cites·8 claims
- 1076US6430657B1Computer system that provides atomicity by using a tlb to indicate whether an exportable instruction should be executed using cache coherency or by exporting the exportable instruction, and emulates instructions specifying a bus lockINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Aug 6, 2002·80 cites·6 claims
- 1174US6138135APropagating NaNs during high precision calculations using lesser precision hardwareINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Oct 24, 2000·64 cites·17 claims
- 1274US6128706AApparatus and method for a load bias--load with intent to semaphoreINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Oct 3, 2000·68 cites·15 claims
- 1372US6301705B1System and method for deferring exceptions generated during speculative executionINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Oct 9, 2001·59 cites·17 claims
- 1472US6212603B1Processor with apparatus for tracking prefetch and demand fetch instructions serviced by cache memoryINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Apr 3, 2001·77 cites·28 claims
- 1570US6293712B1Method and apparatus for constructing a stack unwind data structureINST THE DEV OF EMERGING ARCHI·Filed 1997·Granted Sep 25, 2001·58 cites·9 claims
- 1670US5809563AMethod and apparatus utilizing a region based page table walk bitINST THE DEV OF EMERGING ARCHI·Filed 1996·Granted Sep 15, 1998·43 cites·13 claims
- 1770US5664148ACache arrangement including coalescing buffer queue for non-cacheable dataINST THE DEV OF EMERGING ARCHI·Filed 1995·Granted Sep 2, 1997·59 cites·8 claims
- 1869US6408373B2Method and apparatus for pre-validating regions in a virtual addressing schemeINST THE DEV OF EMERGING ARCHI·Filed 2001·Granted Jun 18, 2002·12 cites·7 claims
- 1967US6665793B1Method and apparatus for managing access to out-of-frame RegistersINST THE DEV OF EMERGING ARCHI·Filed 1999·Granted Dec 16, 2003·37 cites·20 claims
- 2066US5915117AComputer architecture for the deferral of exceptions on speculative instructionsINST THE DEV OF EMERGING ARCHI·Filed 1997·Granted Jun 22, 1999·49 cites·34 claims
- 2165US6249798B1Method, apparatus and computer system for directly transferring and translating data between an integer processing unit and a floating point processing unitINST THE DEV OF EMERGING ARCHI·Filed 1996·Granted Jun 19, 2001·26 cites·30 claims
- 2265US6012134AHigh-performance processor with streaming buffer that facilitates prefetching of instructionsINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Jan 4, 2000·55 cites·16 claims
- 2364US6119218AMethod and apparatus for prefetching data in a computer systemINST THE DEV OF EMERGING ARCHI·Filed 1999·Granted Sep 12, 2000·37 cites·18 claims
- 2463US6216214B1Apparatus and method for a virtual hashed page tableINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Apr 10, 2001·34 cites·17 claims
- 2563US5903749AMethod and apparatus for implementing check instructions that allow for the reuse of memory conflict information if no memory conflict occursINST THE DEV OF EMERGING ARCHI·Filed 1996·Granted May 11, 1999·51 cites·37 claims
- 2662US6006325AMethod and apparatus for instruction and data serialization in a computer processorINST THE DEV OF EMERGING ARCHI·Filed 1996·Granted Dec 21, 1999·39 cites·17 claims
- 2753US6269438B1Method for identifying hard-to-predict branches to enhance processor performanceINST THE DEV OF EMERGING ARCHI·Filed 1999·Granted Jul 31, 2001·25 cites·10 claims
- 2853US5928356AMethod and apparatus for selectively controlling groups of registersINST THE DEV OF EMERGING ARCHI·Filed 1997·Granted Jul 27, 1999·27 cites·17 claims
- 2952US5848256AMethod and apparatus for address disambiguation using address component identifiersINST THE DEV OF EMERGING ARCHI·Filed 1996·Granted Dec 8, 1998·25 cites·19 claims
- 3050US6370639B1Processor architecture having two or more floating-point status fieldsINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Apr 9, 2002·23 cites·43 claims
- 3150US6330691B1Use of dynamic translation to provide breakpoints in non-writeable object codeINST THE DEV OF EMERGING ARCHI·Filed 1996·Granted Dec 11, 2001·23 cites·14 claims
- 3248US6578059B1Methods and apparatus for controlling exponent range in floating-point calculationsINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Jun 10, 2003·20 cites·22 claims
- 3342US6263401B1Method and apparatus for transferring data between a register stack and a memory resourceINST THE DEV OF EMERGING ARCHI·Filed 1997·Granted Jul 17, 2001·13 cites·22 claims
- 3442US6230248B1Method and apparatus for pre-validating regions in a virtual addressing schemeINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted May 8, 2001·14 cites·1 claims
- 3541US6212539B1Methods and apparatus for handling and storing bi-endian words in a floating-point processorINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Apr 3, 2001·13 cites·14 claims
- 3639US6408380B1Execution of an instruction to load two independently selected registers in a single cycleINST THE DEV OF EMERGING ARCHI·Filed 1999·Granted Jun 18, 2002·10 cites·30 claims
- 3736US6009263AEmulating agent and method for reformatting computer instructions into a standard uniform formatINST THE DEV OF EMERGING ARCHI·Filed 1997·Granted Dec 28, 1999·10 cites·14 claims
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