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INTRINSITY INC
US69 patents
Top patents by PatentIndex Score
US6260131B1Jul 10, 2001
Method and apparatus for TLB memory ordering
INTRINSITY INC133 citations97
US6567835B1May 20, 2003
Method and apparatus for a 5:2 carry-save-adder (CSA)
INTRINSITY INC62 citations96
US6457170B1Sep 24, 2002
Software system build method and apparatus that supports multiple users in a software development environment
INTRINSITY INC91 citations96
US6275838B1Aug 14, 2001
Method and apparatus for an enhanced floating point unit with graphics and integer capabilities
INTRINSITY INC59 citations96
US7219326B2May 15, 2007
Physical realization of dynamic logic using parameterized tile partitioning
INTRINSITY INC198 citations95
US6370632B1Apr 9, 2002
Method and apparatus that enforces a regional memory model in hierarchical memory systems
INTRINSITY INC63 citations95
US6438743B1Aug 20, 2002
Method and apparatus for object cache registration and maintenance in a networked software development environment
INTRINSITY INC66 citations94
US6557021B1Apr 29, 2003
Rounding anticipator for floating point operations
INTRINSITY INC23 citations93
US6460134B1Oct 1, 2002
Method and apparatus for a late pipeline enhanced floating point unit
INTRINSITY INC24 citations93
US6349387B1Feb 19, 2002
Dynamic adjustment of the clock rate in logic circuits
INTRINSITY INC17 citations93
US6288589B1Sep 11, 2001
Method and apparatus for generating clock signals
INTRINSITY INC29 citations93
US6211456B1Apr 3, 2001
Method and apparatus for routing 1 of 4 signals
INTRINSITY INC34 citations93
US6209076B1Mar 27, 2001
Method and apparatus for two-stage address generation
INTRINSITY INC29 citations93
US6202194B1Mar 13, 2001
Method and apparatus for routing 1 of N signals
INTRINSITY INC20 citations93
US6181596B1Jan 30, 2001
Method and apparatus for a RAM circuit having N-Nary output interface
INTRINSITY INC21 citations93
US6118304ASep 12, 2000
Method and apparatus for logic synchronization
INTRINSITY INC33 citations93
US6107835AAug 22, 2000
Method and apparatus for a logic circuit with constant power consumption
INTRINSITY INC36 citations93
US6604065B1Aug 5, 2003
Multiple-state simulation for non-binary logic
INTRINSITY INC27 citations92
US6301600B1Oct 9, 2001
Method and apparatus for dynamic partitionable saturating adder/subtractor
INTRINSITY INC46 citations92
US6275841B1Aug 14, 2001
1-of-4 multiplier
INTRINSITY INC33 citations92
US6272653B1Aug 7, 2001
Method and apparatus for built-in self-test of logic circuitry
INTRINSITY INC86 citations92
US6367065B1Apr 2, 2002
Method and apparatus for N-Nary logic circuit design tool with precharge circuit evaluation
INTRINSITY INC23 citations91
US6898691B2May 24, 2005
Rearranging data between vector and matrix forms in a SIMD matrix processor
INTRINSITY INC42 citations90
US6622240B1Sep 16, 2003
Method and apparatus for pre-branch instruction
INTRINSITY INC30 citations86
US7031897B1Apr 18, 2006
Software modeling of logic signals capable of holding more than two values
INTRINSITY INC11 citations84
US6956406B2Oct 18, 2005
Static storage element for dynamic logic
INTRINSITY INC15 citations84
US6334183B1Dec 25, 2001
Method and apparatus for handling partial register accesses
INTRINSITY INC17 citations84
US6271683B1Aug 7, 2001
Dynamic logic scan gate method and apparatus
INTRINSITY INC16 citations84
US6345381B1Feb 5, 2002
Method and apparatus for a logic circuit design tool
INTRINSITY INC19 citations82
US6594803B1Jul 15, 2003
Method and apparatus that reports multiple status events with a single monitor
INTRINSITY INC15 citations76
US6911846B1Jun 28, 2005
Method and apparatus for a 1 of N signal
INTRINSITY INC11 citations74
US6745357B2Jun 1, 2004
Dynamic logic scan gate method and apparatus
INTRINSITY INC8 citations74
US6404233B1Jun 11, 2002
Method and apparatus for logic circuit transition detection
INTRINSITY INC7 citations74
US6360315B1Mar 19, 2002
Method and apparatus that supports multiple assignment code
INTRINSITY INC7 citations74
US6347327B1Feb 12, 2002
Method and apparatus for N-nary incrementor
INTRINSITY INC7 citations74
US6334136B1Dec 25, 2001
Dynamic 3-level partial result merge adder
INTRINSITY INC8 citations74
US6268746B1Jul 31, 2001
Method and apparatus for logic synchronization
INTRINSITY INC10 citations74
US6252425B1Jun 26, 2001
Method and apparatus for an N-NARY logic circuit
INTRINSITY INC5 citations74
US6233707B1May 15, 2001
Method and apparatus that allows the logic state of a logic gate to be tested when stopping or starting the logic gate's clock
INTRINSITY INC12 citations74
US6216147B1Apr 10, 2001
Method and apparatus for an N-nary magnitude comparator
INTRINSITY INC7 citations74
US6185593B1Feb 6, 2001
Method and apparatus for parallel normalization and rounding technique for floating point arithmetic operations
INTRINSITY INC7 citations74
US6175847B1Jan 16, 2001
Shifting for parallel normalization and rounding technique for floating point arithmetic operations
INTRINSITY INC13 citations74
US6151615ANov 21, 2000
Method and apparatus for formatting an intermediate result for parallel normalization and rounding technique for floating point arithmetic operations
INTRINSITY INC7 citations74
US6104642AAug 15, 2000
Method and apparatus for 1 of 4 register file design
INTRINSITY INC12 citations74
US7099812B2Aug 29, 2006
Grid that tracks the occurrence of a N-dimensional matrix of combinatorial events in a simulation using a linear index
INTRINSITY INC9 citations73
US6728654B2Apr 27, 2004
Random number indexing method and apparatus that eliminates software call sequence dependency
INTRINSITY INC11 citations73
US6289497B1Sep 11, 2001
Method and apparatus for N-NARY hardware description language
INTRINSITY INC10 citations72
US6732346B2May 4, 2004
Generation of route rules
INTRINSITY INC9 citations70
US7299461B2Nov 20, 2007
Expansion syntax
INTRINSITY INC2 citations63
US6415405B1Jul 2, 2002
Method and apparatus for scan of synchronized dynamic logic using embedded scan gates
INTRINSITY INC3 citations63
Showing the top 50 of 69 patents by PatentIndex Score.