Method and apparatus for N-NARY hardware description language

Abstract

A syntax statement describing an N-NARY or a CMOS logic circuit having one, and only one, possible configuration of transistors is disclosed. The syntax statement comprises a signal naming convention and one or more gate instantiations using a gate instantiation syntax that includes one or more gate output signal variables described using the signal naming convention, one or more gate operators, and one or more gate expressions using a gate expression syntax that is interpreted to describe the specific transistor configuration of the logic circuit. The signal naming convention includes one or more of the following fields: optional bit and descriptor, signal degree, evaluation, and clock phase. The gate expression syntax further comprises one or more of the following syntaxes: mux select, arithmetic, logical, multiple output, capacitance isolation, or shared node.

We claim the following invention:  
     
       1. A syntax statement that describes the logical and physical characteristics of a logic gate, comprising: 
       a signal naming convention; and  
       one or more gate instantiations that are built according to said signal naming convention wherein the logical and physical characteristics of the logic gate are described.  
     
     
       2. The syntax statement of claim  1  wherein said signal naming convention further comprises one or more of the following: an optional bit field, an optional descriptor field, a signal degree field, an evaluation field, and a clock phase field. 
     
     
       3. The syntax statement of claim  1  wherein said gate instantiations further comprises one or more gate output signal variables, one or more gate operators, and one or more gate expressions. 
     
     
       4. The syntax statement of claim  3  wherein said gate expression further comprises one or more of the following: a mux select expression, an arithmetic expression, a logical expression, a multiple output expression, a capacitance isolation expression, or a shared node expression. 
     
     
       5. The syntax statement of claim  3  wherein said gate output signal variable further comprises one or more of the following: an optional bit field, an optional descriptor field, a signal degree field, an evaluation field, and a clock phase field. 
     
     
       6. The syntax statement of claim  1  wherein said signal naming convention describes N-nary logic and said gate instantiations describe one or more N-nary logic circuits. 
     
     
       7. The syntax statement of claim  1  wherein said signal naming convention describes CMOS logic and said gate instantiations describe one or more CMOS logic circuits. 
     
     
       8. A system that describes the logical and physical characteristics of a logic gate, comprising: 
       a signal naming convention; and  
       one or more gate instantiations that are built according to said signal naming convention wherein the logical and physical characteristics of the logic gate are described.  
     
     
       9. The system of claim  8  wherein said signal naming convention further comprises one or more of the following: an optional bit field, an optional descriptor field, a signal degree field, an evaluation field, and a clock phase field. 
     
     
       10. The system of claim  8  wherein said gate instantiations further comprises one or more gate output signal variables, one or more gate operators, and one or more gate expressions. 
     
     
       11. The system of claim  10  wherein said gate output signal variable further comprises one or more of the following: an optional bit field, an optional descriptor field, a signal degree field, an evaluation field, and a clock phase field. 
     
     
       12. The system of claim  10  wherein said gate expression further comprises one or more of the following: a mux select expression, an arithmetic expression, a logical expression, a multiple output expression, a capacitance isolation expression, or a shared node expression. 
     
     
       13. The system of claim  8  wherein said signal naming convention describes N-nary logic and said gate instantiations describe one or more N-nary logic circuits. 
     
     
       14. The system of claim  8  wherein said signal naming convention describes CMOS logic and said gate instantiations describe one or more CMOS logic circuits. 
     
     
       15. A method of making a syntax statement that describes the logical and physical characteristics of a logic gate, comprising: 
       providing a signal naming convention; and  
       providing one or more gate instantiations that are built according to said signal naming convention wherein the logical and physical characteristics of the logic gate are described.  
     
     
       16. The method of claim  15  wherein said signal naming convention further comprises one or more of the following: an optional bit field, an optional descriptor field, a signal degree field, an evaluation field, and a clock phase field. 
     
     
       17. The method of claim  15  wherein said gate instantiations further comprises one or more gate output signal variables, one or more gate operators, and one or more gate expressions. 
     
     
       18. The method of claim  17  wherein said gate output signal variable further comprises one or more of the following: an optional bit field, an optional descriptor field, a signal degree field, an evaluation field, and a clock phase field. 
     
     
       19. The method of claim  17  wherein said signal naming convention describes N-nary logic and said gate instantiations describe one or more N-nary logic circuits. 
     
     
       20. The method of claim  17  wherein said signal naming convention describes CMOS logic and said gate instantiations describe one or more CMOS logic circuits. 
     
     
       21. The method of claim  17  wherein said gate expression further comprises one or more of the following: a mux select expression, an arithmetic expression, a logical expression, a multiple output expression, a capacitance isolation expression, or a shared node expression. 
     
     
       22. A method of using a syntax statement that describes the logical and physical characteristics of a logic gate, comprising: 
       providing a signal naming convention; and  
       building one or more gate instantiations according to said signal naming convention wherein the logical and physical characteristics of the logic gate are described.  
         23 .The method of claim  22  wherein said signal naming convention further comprises one or more of the following: an optional bit field, an optional descriptor field, a signal degree field, a evaluation field, and a clock phase field. 
     
     
       24. The method of claim  22  wherein said gate instantiations further comprises one or more gate output signal variables, one or more gate operators, and one or more gate expressions. 
     
     
       25. The method of claim  24  wherein said gate output signal variable further comprises one or more of the following: an optional bit field, an optional descriptor field, a signal degree field, an evaluation field, and a clock phase field. 
     
     
       26. The method of claim  24  wherein said gate expression further comprises one or more of the following: a mux select expression, an arithmetic expression, a logical expression, a multiple output expression, a capacitance isolation expression, or a shared node expression. 
     
     
       27. The method of claim  22  wherein said signal naming convention describes N-nary logic and said gate instantiations describe one or more N-nary logic circuits. 
     
     
       28. The method of claim  22  wherein said signal naming convention describes CMOS logic and said gate instantiations describe one or more CMOS logic circuits. 
     
     
       29. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for using a syntax statement that describes the logical and physical characteristics of a logic gate, comprising: 
       providing a signal naming convention; and  
       building one or more gate instantiations according to said signal naming convention wherein the logical and physical characteristics of the logic gate are described.  
     
     
       30. The program storage device of claim  29 , wherein said signal naming convention further comprises one or more of the following: an optional bit field, an optional descriptor field, a signal degree field, an evaluation field, and a clock phase field. 
     
     
       31. The program storage device of claim  29  wherein said gate instantiations further comprises one or more gate output signal variables, one or more gate operators, and one or more gate expressions. 
     
     
       32. The program storage device of claim  31  wherein said gate output signal variable further comprises one or more of the following: an optional bit field, an optional descriptor field, a signal degree field, an evaluation field, and a clock phase field. 
     
     
       33. The program storage device of claim  31  wherein said gate expression further comprises one or more of the following: a mux select expression, an arithmetic expression, a logical expression, a multiple output expression, a capacitance isolation expression, or a shared node expression. 
     
     
       34. The program storage device of claim  29  wherein said signal naming convention describes N-nary logic and said gate instantiations describe one or more N-nary logic circuits. 
         35 .The program storage device of claim  29  wherein said signal naming convention describes CMOS logic and said gate instantiations describe one or more CMOS logic circuits.