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LIN MOU-SHIUNG
TW81 patents
Top patents by PatentIndex Score
US8503186B2Aug 6, 2013
System-in packages
LIN MOU-SHIUNG143 citations99
US8456856B2Jun 4, 2013
Integrated circuit chip using top post-passivation technology and bottom structure technology
LIN MOU-SHIUNG138 citations98
US8164171B2Apr 24, 2012
System-in packages
LIN MOU-SHIUNG95 citations98
US8148806B2Apr 3, 2012
Multiple chips bonded to packaging structure with low noise and multiple selectable functions
LIN MOU-SHIUNG46 citations97
US6965165B2Nov 15, 2005
Top layers of metal for high performance IC's
LIN MOU-SHIUNG38 citations97
US7482693B2Jan 27, 2009
Top layers of metal for high performance IC's
LIN MOU-SHIUNG24 citations96
US7396756B2Jul 8, 2008
Top layers of metal for high performance IC's
LIN MOU-SHIUNG15 citations96
US7388292B2Jun 17, 2008
Top layers of metal for high performance IC's
LIN MOU-SHIUNG15 citations96
US7385291B2Jun 10, 2008
Top layers of metal for high performance IC's
LIN MOU-SHIUNG14 citations96
US7384864B2Jun 10, 2008
Top layers of metal for high performance IC's
LIN MOU-SHIUNG19 citations96
US7382052B2Jun 3, 2008
Post passivation interconnection schemes on top of IC chip
LIN MOU-SHIUNG20 citations96
US7372085B2May 13, 2008
Top layers of metal for high performance IC's
LIN MOU-SHIUNG16 citations96
US7372155B2May 13, 2008
Top layers of metal for high performance IC's
LIN MOU-SHIUNG19 citations96
US7368376B2May 6, 2008
Top layers of metal for high performance IC's
LIN MOU-SHIUNG15 citations96
US7358610B2Apr 15, 2008
Top layers of metal for high performance IC's
LIN MOU-SHIUNG17 citations96
US7329954B2Feb 12, 2008
Top layers of metal for high performance IC's
LIN MOU-SHIUNG20 citations96
US7294870B2Nov 13, 2007
Top layers of metal for high performance IC's
LIN MOU-SHIUNG17 citations96
US8421227B2Apr 16, 2013
Semiconductor chip structure
LIN MOU-SHIUNG27 citations93
US8193555B2Jun 5, 2012
Image and light sensor chip packages
LIN MOU-SHIUNG29 citations93
US8188603B2May 29, 2012
Post passivation interconnection schemes on top of IC chip
LIN MOU-SHIUNG8 citations93
US8159070B2Apr 17, 2012
Chip packages
LIN MOU-SHIUNG20 citations93
US7465975B2Dec 16, 2008
Top layers of metal for high performance IC's
LIN MOU-SHIUNG10 citations93
US7456100B2Nov 25, 2008
Top layers of metal for high performance IC's
LIN MOU-SHIUNG9 citations93
US7442969B2Oct 28, 2008
Top layers of metal for high performance IC's
LIN MOU-SHIUNG10 citations93
US7425764B2Sep 16, 2008
Top layers of metal for high performance IC's
LIN MOU-SHIUNG11 citations93
US7422976B2Sep 9, 2008
Top layers of metal for high performance IC's
LIN MOU-SHIUNG10 citations93
US7397135B2Jul 8, 2008
Top layers of metal for high performance IC's
LIN MOU-SHIUNG13 citations93
US7385292B2Jun 10, 2008
Top layers of metal for high performance IC's
LIN MOU-SHIUNG14 citations93
US7382058B2Jun 3, 2008
Top layers of metal for high performance IC's
LIN MOU-SHIUNG14 citations93
US7360005B2Apr 15, 2008
Software programmable multiple function integrated circuit module
LIN MOU-SHIUNG31 citations93
US7294871B2Nov 13, 2007
Top layers of metal for high performance IC's
LIN MOU-SHIUNG11 citations93
US8884433B2Nov 11, 2014
Circuitry component and method for forming the same
LIN MOU-SHIUNG23 citations92
US8399989B2Mar 19, 2013
Metal pad or metal bump over pad exposed by passivation layer
LIN MOU-SHIUNG20 citations92
US8187965B2May 29, 2012
Wirebond pad for semiconductor chip or wafer
LIN MOU-SHIUNG20 citations92
US9391021B2Jul 12, 2016
Chip package and method for fabricating the same
LIN MOU-SHIUNG10 citations84
US9030029B2May 12, 2015
Chip package with die and substrate
LIN MOU-SHIUNG7 citations84
US8558383B2Oct 15, 2013
Post passivation structure for a semiconductor device and packaging process for same
LIN MOU-SHIUNG16 citations84
US8552559B2Oct 8, 2013
Very thick metal interconnection scheme in IC chips
LIN MOU-SHIUNG9 citations84
US8487400B2Jul 16, 2013
High performance system-on-chip using post passivation process
LIN MOU-SHIUNG5 citations84
US8471388B2Jun 25, 2013
Integrated circuit and method for fabricating the same
LIN MOU-SHIUNG15 citations84
US8471361B2Jun 25, 2013
Integrated chip package structure using organic substrate and method of manufacturing the same
LIN MOU-SHIUNG7 citations84
US8440272B2May 14, 2013
Method for forming post passivation Au layer with clean surface
LIN MOU-SHIUNG9 citations84
US8426958B2Apr 23, 2013
Stacked chip package with redistribution lines
LIN MOU-SHIUNG5 citations84
US8421158B2Apr 16, 2013
Chip structure with a passive device and method for forming the same
LIN MOU-SHIUNG8 citations84
US8319354B2Nov 27, 2012
Semiconductor chip with post-passivation scheme formed over passivation layer
LIN MOU-SHIUNG8 citations84
US8304907B2Nov 6, 2012
Top layers of metal for integrated circuits
LIN MOU-SHIUNG8 citations84
US8232192B2Jul 31, 2012
Process of bonding circuitry components
LIN MOU-SHIUNG8 citations84
US8211791B2Jul 3, 2012
Method for fabricating circuitry component
LIN MOU-SHIUNG11 citations84
US8178435B2May 15, 2012
High performance system-on-chip inductor using post passivation process
LIN MOU-SHIUNG17 citations84
US8158508B2Apr 17, 2012
Structure and manufacturing method of a chip scale package
LIN MOU-SHIUNG13 citations84
Showing the top 50 of 81 patents by PatentIndex Score.