Assignee

PDF SOLUTIONS INC

US190 patents

Top patents by PatentIndex Score

US7592827B1Sep 22, 2009

Apparatus and method for electrical detection and localization of shorts in metal interconnect lines

PDF SOLUTIONS INC114 citations99

US9496119B1Nov 15, 2016

E-beam inspection apparatus and method of using the same on various integrated circuit chips

PDF SOLUTIONS INC77 citations98

US6901564B2May 31, 2005

System and method for product yield prediction

PDF SOLUTIONS INC143 citations98

US6834375B1Dec 21, 2004

System and method for product yield prediction using a logic characterization vehicle

PDF SOLUTIONS INC246 citations98

US6826738B2Nov 30, 2004

Optimization of die placement on wafers

PDF SOLUTIONS INC213 citations98

US6795952B1Sep 21, 2004

System and method for product yield prediction using device and process neighborhood characterization vehicle

PDF SOLUTIONS INC264 citations98

US6449749B1Sep 10, 2002

System and method for product yield prediction

PDF SOLUTIONS INC202 citations98

US7739065B1Jun 15, 2010

Inspection plan optimization based on layout attributes and process variance

PDF SOLUTIONS INC89 citations97

US9870962B1Jan 16, 2018

Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

PDF SOLUTIONS INC13 citations96

US7174521B2Feb 6, 2007

System and method for product yield prediction

PDF SOLUTIONS INC32 citations96

US7487474B2Feb 3, 2009

Designing an integrated circuit to improve yield using a variant design element

PDF SOLUTIONS INC182 citations95

US7278118B2Oct 2, 2007

Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features

PDF SOLUTIONS INC212 citations94

US9805994B1Oct 31, 2017

Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads

PDF SOLUTIONS INC15 citations93

US9799575B2Oct 24, 2017

Integrated circuit containing DOEs of NCEM-enabled fill cells

PDF SOLUTIONS INC19 citations93

US9627370B1Apr 18, 2017

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells

PDF SOLUTIONS INC15 citations93

US7673262B2Mar 2, 2010

Methodology for the optimization of testing and diagnosis of analog and mixed signal ICs and embedded cores

PDF SOLUTIONS INC26 citations91

US7902852B1Mar 8, 2011

High density test structure array to support addressable high accuracy 4-terminal measurements

PDF SOLUTIONS INC19 citations90

US7434197B1Oct 7, 2008

Method for improving mask layout and fabrication

PDF SOLUTIONS INC21 citations90

US6978229B1Dec 20, 2005

Efficient method for modeling and simulation of the impact of local and global variation on integrated circuits

PDF SOLUTIONS INC53 citations89

US7047505B2May 16, 2006

Method for optimizing the characteristics of integrated circuits components from circuit specifications

PDF SOLUTIONS INC19 citations88

US10978438B1Apr 13, 2021

IC with test structures and E-beam pads embedded within a contiguous standard cell area

PDF SOLUTIONS INC9 citations86

US10768222B1Sep 8, 2020

Method and apparatus for direct testing and characterization of a three dimensional semiconductor memory structure

PDF SOLUTIONS INC13 citations86

US10593604B1Mar 17, 2020

Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells

PDF SOLUTIONS INC19 citations86

US7415386B2Aug 19, 2008

Method and system for failure signal detection analysis

PDF SOLUTIONS INC22 citations86

US11295993B2Apr 5, 2022

Maintenance scheduling for semiconductor manufacturing equipment

PDF SOLUTIONS INC6 citations84

US10199283B1Feb 5, 2019

Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage

PDF SOLUTIONS INC3 citations84

US10199288B1Feb 5, 2019

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one side-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective side-to-side short, corner short, and via open test areas

PDF SOLUTIONS INC2 citations84

US9905487B1Feb 27, 2018

Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of V0 via opens

PDF SOLUTIONS INC3 citations84

US9786648B1Oct 10, 2017

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells

PDF SOLUTIONS INC2 citations84

US9773773B1Sep 26, 2017

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and GATECNT-short-configured, NCEM-enabled fill cells

PDF SOLUTIONS INC2 citations84

US9761575B1Sep 12, 2017

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells

PDF SOLUTIONS INC2 citations84

US9741703B1Aug 22, 2017

Integrated circuit containing standard logic cells and ilbrary-compatible, NCEM-enabled fill cells, including at least via-open-configured, gate-short-configured, TS-short-configured, and AA-short-conigured, NCEM-enabled fill cells

PDF SOLUTIONS INC4 citations84

US9691672B1Jun 27, 2017

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells

PDF SOLUTIONS INC4 citations84

US9627371B1Apr 18, 2017

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cells

PDF SOLUTIONS INC7 citations84

US9595536B1Mar 14, 2017

Standard cell library that includes 13-CPP and 17-CPP D flip-flop cells, with DFM-optimized M0 cuts and V0 adjacencies

PDF SOLUTIONS INC13 citations84

US9461065B1Oct 4, 2016

Standard cell library with DFM-optimized M0 cuts and V0 adjacencies

PDF SOLUTIONS INC10 citations84

US7935965B1May 3, 2011

Test structures and methods for electrical characterization of alignment of line patterns defined with double patterning

PDF SOLUTIONS INC18 citations84

US6787800B2Sep 7, 2004

Test vehicle with zig-zag structures

PDF SOLUTIONS INC18 citations84

US11029673B2Jun 8, 2021

Generating robust machine learning predictions for semiconductor manufacturing processes

PDF SOLUTIONS INC9 citations83

US8037379B1Oct 11, 2011

Prediction of impact on post-repair yield resulting from manufacturing process modification

PDF SOLUTIONS INC7 citations82

US7197726B2Mar 27, 2007

Test structures for estimating dishing and erosion effects in copper damascene technology

PDF SOLUTIONS INC11 citations82

US7024642B2Apr 4, 2006

Extraction method of defect density and size distributions

PDF SOLUTIONS INC16 citations82

US11029359B2Jun 8, 2021

Failure detection and classsification using sensor data and/or measurement data

PDF SOLUTIONS INC8 citations80

US7348594B2Mar 25, 2008

Test structures and models for estimating the yield impact of dishing and/or voids

PDF SOLUTIONS INC12 citations79

US7644388B1Jan 5, 2010

Method for reducing layout printability effects on semiconductor device performance

PDF SOLUTIONS INC9 citations78

US7087507B2Aug 8, 2006

Implantation of deuterium in MOS and DRAM devices

PDF SOLUTIONS INC17 citations78

Showing the top 50 of 190 patents by PatentIndex Score.

PDF SOLUTIONS INC

Top patents by PatentIndex Score

Apparatus and method for electrical detection and localization of shorts in metal interconnect lines

E-beam inspection apparatus and method of using the same on various integrated circuit chips

System and method for product yield prediction

System and method for product yield prediction using a logic characterization vehicle

Optimization of die placement on wafers

System and method for product yield prediction using device and process neighborhood characterization vehicle

System and method for product yield prediction

Inspection plan optimization based on layout attributes and process variance

Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

System and method for product yield prediction

Designing an integrated circuit to improve yield using a variant design element

Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features

Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads

Integrated circuit containing DOEs of NCEM-enabled fill cells

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells

System and method for product yield prediction

System and method for product yield prediction

System and method for product yield prediction

Passive multiplexor test structure for integrated circuit manufacturing

Methodology for the optimization of testing and diagnosis of analog and mixed signal ICs and embedded cores

High density test structure array to support addressable high accuracy 4-terminal measurements

Method for improving mask layout and fabrication

Efficient method for modeling and simulation of the impact of local and global variation on integrated circuits

Method for optimizing the characteristics of integrated circuits components from circuit specifications

IC with test structures and E-beam pads embedded within a contiguous standard cell area

Method and apparatus for direct testing and characterization of a three dimensional semiconductor memory structure

Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells

Method and system for failure signal detection analysis

Maintenance scheduling for semiconductor manufacturing equipment

Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of V0 via opens

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and GATECNT-short-configured, NCEM-enabled fill cells

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells

Integrated circuit containing standard logic cells and ilbrary-compatible, NCEM-enabled fill cells, including at least via-open-configured, gate-short-configured, TS-short-configured, and AA-short-conigured, NCEM-enabled fill cells

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cells

Standard cell library that includes 13-CPP and 17-CPP D flip-flop cells, with DFM-optimized M0 cuts and V0 adjacencies

Standard cell library with DFM-optimized M0 cuts and V0 adjacencies

Test structures and methods for electrical characterization of alignment of line patterns defined with double patterning

Test vehicle with zig-zag structures

Generating robust machine learning predictions for semiconductor manufacturing processes

Prediction of impact on post-repair yield resulting from manufacturing process modification

Test structures for estimating dishing and erosion effects in copper damascene technology

Extraction method of defect density and size distributions

Failure detection and classsification using sensor data and/or measurement data

Test structures and models for estimating the yield impact of dishing and/or voids

Method for reducing layout printability effects on semiconductor device performance

Implantation of deuterium in MOS and DRAM devices