High density test structure array to support addressable high accuracy 4-terminal measurements

Abstract

Circuits for performing four terminal measurement point (TMP) testing of devices under test (DUT) is provided. The DUT and the circuit is to be defined on a semiconductor chip. The circuit includes a DUT having a first terminal and a second terminal, where the first terminal of the DUT is connectable to a first terminal measurement point and a third terminal measurement point, and the second terminal of the DUT is connectable to a second terminal measurement point and a fourth terminal measurement point. A first transistor is provided to select access to the first terminal measurement point, a second transistor is provided to select access to the third terminal measurement point, a third transistor is provided to select access to the second terminal measurement point; and a fourth transistor is provided to select access to the fourth terminal measurement point. In one example, the DUT is linked to neighboring DUTs, and selected ones of the first through fourth transistors are shared, thus reducing the number of transistors per DUT in a DUT bank, and reducing the area needed to implement DUT bank testing for addressable 4-TMP testing. The compact circuitry further enables DUT bank stacking in rows, addressing of columns of DUTs for conditional testing, and three dimensional stacking of DUT banks on different levels.

1. A circuit for performing four terminal measurement point (TMP) testing of devices under test (DUT) comprising:
 a first transistor providing selectable access to a first terminal measurement point operable to be connected to a first terminal of said DUT; 
 a second transistor providing selectable access to a third terminal measurement point operable to be connected to said first terminal of said DUT; 
 a third transistor providing selectable access to a second terminal measurement point operable to be connected to a second terminal of said DUT; and 
 a fourth transistor providing selectable access to a fourth terminal measurement point operable to be connected to said second terminal of said DUT, 
 wherein said first terminal measurement point, said second terminal measurement point, said third terminal measurement point, and said fourth terminal measurement point form distinct electrical nodes from each other. 
 
     
     
       2. A circuit as recited in  claim 1 , wherein the first transistor comprises a first source/drain and a second source/drain, and wherein the second transistor comprises a first source/drain and a second source/drain, and wherein the first source/drain of the first transistor and the first source/drain of the second transistor are linked together and operable to be coupled to the first terminal of the DUT, wherein the second source/drain of the first transistor is connected to the first terminal measurement point, and wherein the second source/drain of the second transistor is connected to the third terminal measurement point. 
     
     
       3. A circuit as recited in  claim 1 , wherein the third transistor comprises a first source/drain and a second source/drain, and wherein the fourth transistor comprises a first source/drain and a second source/drain, wherein the first source/drain of the third transistor and the first source/drain of the fourth transistor are linked together and operable to be coupled to the second terminal of the DUT, wherein the second source/drain of the third transistor is connected to the fourth terminal measurement point, and wherein the second source/drain of the fourth transistor is connected to the second terminal measurement point. 
     
     
       4. A circuit as recited in  claim 1  further comprising:
 a fifth transistor operable for providing a selectable access to a second terminal measurement point of a first adjacent DUT, wherein said first adjacent DUT comprises a first terminal and a second terminal; and 
 a sixth transistor operable for providing a selectable access to a fourth terminal measurement point of said first adjacent DUT; 
 wherein the first transistor and the second transistor of the DUT are shared with said first adjacent DUT, wherein said sharing is operable to provide to enable access to a first terminal measurement point and a third terminal measurement point of said first adjacent DUT. 
 
     
     
       5. A circuit as recited in  claim 4  further comprising:
 a seventh transistor operable for providing a selectable access to a first terminal measurement point of a second adjacent DUT, wherein said second adjacent DUT is next to said first adjacent DUT, and wherein said second adjacent DUT comprises a first and a second terminal; and 
 an eight transistor operable for providing a selectable access to a third terminal measurement point of said second adjacent DUT; 
 wherein the fifth transistor and the sixth transistor of the first adjacent DUT are shared with said second adjacent DUT, wherein said sharing is operable to provide access to a fourth terminal measurement point and a second terminal measurement point of said second adjacent DUT. 
 
     
     
       6. A circuit as recited in  claim 5 , wherein the DUT is a first DUT, the first adjacent DUT is a second DUT, and the second adjacent DUT is a third DUT, and wherein the first, second and third DUT are capable of being linked together if the first, second, third, fourth, fifth, sixth, seventh, and eighth transistors are addressed to enable the first, second and third DUTs to be serially linked, and the first, second, third, fourth, fifth, sixth, seventh, and eighth transistors being conditionally addressable to enable access to only selected ones of the first, second and third DUTs. 
     
     
       7. A circuit as recited in  claim 6 , wherein the first, second and third DUTs are operable to form a bank of DUTs. 
     
     
       8. A circuit as recited in  claim 7 , wherein each DUT in the bank of DUTs is addressable to enable soft fail analysis and hard fail detection. 
     
     
       9. A circuit as recited in  claim 7  further comprising:
 the bank of DUTs; and 
 a second bank of DUTs; 
 wherein the bank of DUTs and the second bank of DUTs are operable to be alternatively selected using a plurality of first stage selection transistors, the plurality of first stage selection transistors operable for enabling access to the first, second, third, and fourth terminal measurement points of the bank of DUTs or the second bank of DUTs. 
 
     
     
       10. A circuit as recited in  claim 9  further comprising:
 a first array of banks defined by the bank of DUTs and the second bank of DUTs; and 
 a second array of banks defined by two or more banks of DUTs; 
 wherein the first array of banks and the second array of banks are operable to be alternatively selected using a plurality of second stage selection transistors, the plurality of second stage selection transistors operable for enabling access to third and fourth terminal measurement points, and wherein first and second terminal measurements points associated with each of the first and second array of banks is unique. 
 
     
     
       11. A circuit as recited in  claim 10 , wherein the third and fourth terminal measurement points define a voltage path, and wherein each of the first and second terminal measurement points defines a current path. 
     
     
       12. A circuit as recited in  claim 7 , wherein the bank of DUTs is arranged in a stacked orientation comprising two or more rows of DUTs, and each adjacent DUT of said bank of DUTs shares first column selection logic,
 wherein access to each of the two or more rows and access to the first, second, third, and fourth terminal measurement points is provided through second stage selection devices, and wherein second stage row selection logic is operable for selecting one of the two or more rows for being connected to the first, second, third, and fourth terminal measurement points. 
 
     
     
       13. A circuit for four terminal measurement point (TMP) testing of devices under test (DUT) comprising:
 a pair of p-type access transistors, a terminal of each of the pair of p-type access transistors operable for coupling to a first end of the DUT and the other ends of the pair of p-type access transistors operable for coupling to each of a first terminal measurement point and a third terminal measurement point of said DUT; 
 a pair of n-type access transistors, a terminal of each of the pair of n-type access transistors operable for coupling to a second end of the DUT and the other ends of the pair of n-type access transistors being coupled to each of a fourth terminal measurement point and a second terminal measurement point of said DUT, 
 wherein said first terminal measurement point, said second terminal measurement point, said third terminal measurement point, and said fourth terminal measurement point form distinct electrical nodes from each other. 
 
     
     
       14. A circuit as recited in  claim 13 , wherein DUTs are operable to be arranged in a bank of two or more DUTs, and wherein each DUT of the two or more DUTs share either the pair of p-type access transistors or the pair of n-type access transistors. 
     
     
       15. A circuit as recited in  claim 13 , wherein the pair of p-type access transistors and the pair of n-type access transistors have their gates coupled together and connected to bank selection logic, the bank selection logic operable to define a condition for testing DUT in a bank of DUTs. 
     
     
       16. A circuit as recited in  claim 15  further comprising:
 first stage selection transistors operable to enable selection of either the bank of DUTs or a second bank of DUTs, wherein said second bank of DUTs is duplicate of said bank of DUTs, and wherein the first stage selection transistors are operable to provide access to the first, second, third and fourth terminal measurement points. 
 
     
     
       17. A circuit as recited in  claim 16 , further comprising:
 second stage selection transistors operable for selecting a first array of banks comprising said bank of DUTs and said second bank of DUTs or a second array of banks. 
 
     
     
       18. A circuit as recited in  claim 17 , wherein the second stage selection transistors are operable to provide access to the third terminal measurement point and the fourth terminal measurement point, and wherein the first array of banks and the second array of banks each has its own first terminal measurement points and second terminal measurement points. 
     
     
       19. A circuit as recited in  claim 16 , wherein the bank of DUTs comprises two or more rows, and wherein each row is independently selectable by second stage row selection logic, and wherein a first stage column select logic is operable to select one or more DUTs in a row of said two or more rows. 
     
     
       20. A circuit for performing four terminal measurement point (TMP) testing of devices under test (DUT) comprising:
 a first transistor providing selectable access to a first terminal measurement point operable to be connected to a first terminal of said DUT; 
 a second transistor providing selectable access to a third terminal measurement point operable to be connected to said first terminal of said DUT; 
 a third transistor providing selectable access to a second terminal measurement point operable to be connected to a second terminal of said DUT; and 
 a fourth transistor providing selectable access to a fourth terminal measurement point operable to be connected to said second terminal of said DUT; 
 wherein the first, second, third and fourth transistors are the only transistors local to the DUT for enabling the four terminal measurement point (TMP) testing, and wherein said first terminal measurement point, said second terminal measurement point, said third terminal measurement point, and said fourth terminal measurement point form distinct electrical nodes from each other.