Assignee
RAMARAJU RAVINDRARAJ
US33 patents
Top patents by PatentIndex Score
US8566836B2Oct 22, 2013
Multi-core system on chip
RAMARAJU RAVINDRARAJ35 citations94
US8493121B1Jul 23, 2013
Reconfigurable flip-flop
RAMARAJU RAVINDRARAJ16 citations93
US9224439B2Dec 29, 2015
Memory with word line access control
RAMARAJU RAVINDRARAJ8 citations84
US8339838B2Dec 25, 2012
In-line register file bitcell
RAMARAJU RAVINDRARAJ16 citations84
US8319548B2Nov 27, 2012
Integrated circuit having low power mode voltage regulator
RAMARAJU RAVINDRARAJ8 citations84
US8677205B2Mar 18, 2014
Hierarchical error correction for large memories
RAMARAJU RAVINDRARAJ11 citations81
US8484523B2Jul 9, 2013
Sequential digital circuitry with test scan
RAMARAJU RAVINDRARAJ12 citations80
US8914712B2Dec 16, 2014
Hierarchical error correction
RAMARAJU RAVINDRARAJ7 citations76
US9081693B2Jul 14, 2015
Data type dependent memory scrubbing
RAMARAJU RAVINDRARAJ4 citations73
US9059687B2Jun 16, 2015
Flip-flop having shared feedback and method of operation
RAMARAJU RAVINDRARAJ5 citations73
US8806294B2Aug 12, 2014
Error detection within a memory
RAMARAJU RAVINDRARAJ6 citations73
US8537625B2Sep 17, 2013
Memory voltage regulator with leakage current voltage control
RAMARAJU RAVINDRARAJ5 citations73
US8489906B2Jul 16, 2013
Data processor having multiple low power modes
RAMARAJU RAVINDRARAJ5 citations73
US8533578B2Sep 10, 2013
Error detection in a content addressable memory (CAM) and method of operation
RAMARAJU RAVINDRARAJ6 citations66
US9081719B2Jul 14, 2015
Selective memory scrubbing based on data type
RAMARAJU RAVINDRARAJ3 citations63
US8791739B2Jul 29, 2014
Flip-flop having shared feedback and method of operation
RAMARAJU RAVINDRARAJ2 citations63
US8542048B2Sep 24, 2013
Double edge triggered flip flop
RAMARAJU RAVINDRARAJ2 citations63
US8487656B1Jul 16, 2013
Dynamic logic circuit
RAMARAJU RAVINDRARAJ3 citations63
US8143929B2Mar 27, 2012
Flip-flop having shared feedback and method of operation
RAMARAJU RAVINDRARAJ3 citations63
US9317087B2Apr 19, 2016
Memory column drowsy control
RAMARAJU RAVINDRARAJ2 citations62
US8099580B2Jan 17, 2012
Translation look-aside buffer with a tag memory and method therefor
RAMARAJU RAVINDRARAJ5 citations56
US9542334B2Jan 10, 2017
Memory management unit TAG memory with CAM evaluate signal
RAMARAJU RAVINDRARAJ0 citations52
US9367475B2Jun 14, 2016
System and method for cache access
RAMARAJU RAVINDRARAJ0 citations52
US9035629B2May 19, 2015
Voltage regulator with different inverting gain stages
RAMARAJU RAVINDRARAJ1 citations52
US8943292B2Jan 27, 2015
System and method for memory array access with fast address decoder
RAMARAJU RAVINDRARAJ0 citations52
US8199547B2Jun 12, 2012
Error detection in a content addressable memory (CAM)
RAMARAJU RAVINDRARAJ1 citations52
US9400711B2Jul 26, 2016
Content addressable memory with error detection
RAMARAJU RAVINDRARAJ0 citations51
US9117507B2Aug 25, 2015
Multistage voltage regulator circuit
RAMARAJU RAVINDRARAJ1 citations51
US9021194B2Apr 28, 2015
Memory management unit tag memory
RAMARAJU RAVINDRARAJ1 citations51
US9117498B2Aug 25, 2015
Memory with power savings for unnecessary reads
RAMARAJU RAVINDRARAJ0 citations42
US8710916B2Apr 29, 2014
Electronic circuit having shared leakage current reduction circuits
RAMARAJU RAVINDRARAJ0 citations42
US9323691B2Apr 26, 2016
Multiple page size memory management unit
RAMARAJU RAVINDRARAJ0 citations39
US9116799B2Aug 25, 2015
Method for detecting bank collision at a memory and device therefor
RAMARAJU RAVINDRARAJ0 citations39