Assignee
TSUKAMOTO YASUTAKA
JP·3 granted patents·3 citations·filing 2006–2011
Technology mixG06F3
Top patents by PatentIndex Score
3 records- 0160USRE43623EMethod and apparatus for simulating logic circuits that include a circuit block to which power is not suppliedTSUKAMOTO YASUTAKA·Filed 2009·Granted Aug 28, 2012·2 cites·21 claims
- 0253US8239834B2Method and system of program development supportingTSUKAMOTO YASUTAKA·Filed 2006·Granted Aug 7, 2012·1 cites·7 claims
- 0339US8701061B2Semiconductor design support apparatusTSUKAMOTO YASUTAKA·Filed 2011·Granted Apr 15, 2014·0 cites·8 claims
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