Assignee
XCELSIS CORP
US42 patents
Top patents by PatentIndex Score
US11348898B2May 31, 2022
Systems and methods for releveled bump planes for chiplets
XCELSIS CORP144 citations99
US11176450B2Nov 16, 2021
Three dimensional circuit implementing machine trained network
XCELSIS CORP144 citations99
US10991804B2Apr 27, 2021
Transistor level interconnection methodologies utilizing 3D interconnects
XCELSIS CORP144 citations99
US10950547B2Mar 16, 2021
Stacked IC structure with system level wiring on multiple sides of the IC die
XCELSIS CORP145 citations99
US10923413B2Feb 16, 2021
Hard IP blocks with physically bidirectional passageways
XCELSIS CORP144 citations99
US10886177B2Jan 5, 2021
3D chip with shared clock distribution network
XCELSIS CORP148 citations99
US10762420B2Sep 1, 2020
Self repairing neural network
XCELSIS CORP30 citations98
US11127738B2Sep 21, 2021
Back biasing of FD-SOI circuit blocks
XCELSIS CORP144 citations97
US10910344B2Feb 2, 2021
Systems and methods for releveled bump planes for chiplets
XCELSIS CORP17 citations94
US10719762B2Jul 21, 2020
Three dimensional chip structure implementing machine trained network
XCELSIS CORP20 citations94
US10672663B2Jun 2, 2020
3D chip sharing power circuit
XCELSIS CORP25 citations94
US10672743B2Jun 2, 2020
3D Compute circuit with high density z-axis interconnects
XCELSIS CORP23 citations94
US10672745B2Jun 2, 2020
3D processor
XCELSIS CORP25 citations94
US10672744B2Jun 2, 2020
3D compute circuit with high density Z-axis interconnects
XCELSIS CORP27 citations94
US10607136B2Mar 31, 2020
Time borrowing between layers of a three dimensional chip stack
XCELSIS CORP21 citations94
US10600780B2Mar 24, 2020
3D chip sharing data bus circuit
XCELSIS CORP21 citations94
US10600735B2Mar 24, 2020
3D chip sharing data bus
XCELSIS CORP21 citations94
US10600691B2Mar 24, 2020
3D chip sharing power interconnect layer
XCELSIS CORP24 citations94
US10593667B2Mar 17, 2020
3D chip with shielded clock lines
XCELSIS CORP22 citations94
US10586786B2Mar 10, 2020
3D chip sharing clock interconnect layer
XCELSIS CORP22 citations94
US10580735B2Mar 3, 2020
Stacked IC structure with system level wiring on multiple sides of the IC die
XCELSIS CORP21 citations94
US10522352B2Dec 31, 2019
Direct-bonded native interconnects and active base die
XCELSIS CORP20 citations94
US10832912B2Nov 10, 2020
Direct-bonded native interconnects and active base die
XCELSIS CORP10 citations93
US10580757B2Mar 3, 2020
Face-to-face mounted IC dies with orthogonal top interconnect layers
XCELSIS CORP25 citations93
US10784282B2Sep 22, 2020
3D NAND—high aspect ratio strings and channels
XCELSIS CORP6 citations84
US10700094B2Jun 30, 2020
Device disaggregation for improved performance
XCELSIS CORP6 citations84
US11469214B2Oct 11, 2022
Stacked architecture for three-dimensional NAND
XCELSIS CORP2 citations73
US11404439B2Aug 2, 2022
3D NAND—high aspect ratio strings and channels
XCELSIS CORP3 citations73
US11289333B2Mar 29, 2022
Direct-bonded native interconnects and active base die
XCELSIS CORP1 citations73
US11152336B2Oct 19, 2021
3D processor having stacked integrated circuit die
XCELSIS CORP4 citations73
US11139283B2Oct 5, 2021
Abstracted NAND logic in stacks
XCELSIS CORP2 citations73
US10978348B2Apr 13, 2021
3D chip sharing power interconnect layer
XCELSIS CORP2 citations73
US10852545B2Dec 1, 2020
Head mounted viewer for AR and VR scenes
XCELSIS CORP1 citations63
US10295588B2May 21, 2019
Wafer testing without direct probing
XCELSIS CORP1 citations63
US11246230B2Feb 8, 2022
Configurable smart object system with methods of making modules and contactors
XCELSIS CORP0 citations62
US11239587B2Feb 1, 2022
Configurable smart object system with clip-based connectors
XCELSIS CORP0 citations62
US11157670B2Oct 26, 2021
Systems and methods for inter-die block level design
XCELSIS CORP0 citations62
US10970627B2Apr 6, 2021
Time borrowing between layers of a three dimensional chip stack
XCELSIS CORP0 citations62
US10892252B2Jan 12, 2021
Face-to-face mounted IC dies with orthogonal top interconnect layers
XCELSIS CORP0 citations62
US10734759B2Aug 4, 2020
Configurable smart object system with magnetic contacts and magnetic assembly
XCELSIS CORP1 citations62
US10684929B2Jun 16, 2020
Self healing compute array
XCELSIS CORP0 citations52
US10664564B2May 26, 2020
Systems and methods for inter-die block level design
XCELSIS CORP0 citations52