Transistor level interconnection methodologies utilizing 3D interconnects

Abstract

A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.

The invention claimed is: 
     
       1. A microelectronic unit, comprising:
 an epitaxial silicon layer having a front silicon surface and a back silicon surface opposite the front silicon surface, the epitaxial silicon layer having a source and a drain each extending between the front and back silicon surfaces, the source and the drain being doped portions of the epitaxial silicon layer; 
 a buried oxide layer having a top oxide surface and a bottom oxide surface opposite the top oxide surface, such that the top oxide surface faces the back silicon surface; and 
 an ohmic contact extending through the buried oxide layer between the top and bottom oxide surfaces, the ohmic contact being physically coupled to a lower surface of one of the source or the drain. 
 
     
     
       2. The microelectronic unit of  claim 1 , further comprising:
 one or more dielectric layers having a first dielectric surface and a second dielectric surface opposite the first dielectric surface, such that the first dielectric surface faces the bottom oxide surface of the buried oxide layer; and 
 a conductive element extending through the one or more dielectric layers between the first and second dielectric surfaces, the conductive element being coupled to a lower surface of the ohmic contact and configured to be coupled to an external component. 
 
     
     
       3. The microelectronic unit of  claim 1 , further comprising an isolation trench extending through the epitaxial silicon layer between the front and back silicon surfaces, the isolation trench being configured to electrically isolate the source and the drain from adjacent portions of the epitaxial silicon layer. 
     
     
       4. The microelectronic unit of  claim 1 , further comprising a front dielectric layer assembly at the front silicon surface of the epitaxial silicon layer, the microelectronic unit being devoid of electrically conductive elements extending through the front dielectric layer assembly to the source or the drain. 
     
     
       5. The microelectronic unit of  claim 1 , further comprising a front dielectric layer assembly at the front silicon surface of the epitaxial silicon layer, the microelectronic unit comprising electrically conductive elements extending through portions of the front dielectric layer and providing electrical connection to other elements on the microelectronic unit. 
     
     
       6. The microelectronic unit of  claim 1 , wherein the ohmic contact is coupled to the lower surface of the one of the source or the drain by a layer of silicide extending between the ohmic contact and the lower surface of the one of the source or the drain. 
     
     
       7. The microelectronic unit of  claim 2 , wherein the conductive element includes a rigid conductive post extending beyond the second dielectric surface of the one or more-dielectric layers, the conductive post configured to be coupled to a corresponding conductive element of the external component. 
     
     
       8. The microelectronic unit of  claim 2 , further comprising a conductive interconnect extending from the front silicon surface of the epitaxial silicon layer to the second dielectric surface of the one or more dielectric layers, the conductive interconnect exposed at the second surface and configured to be bonded to the external component. 
     
     
       9. The microelectronic unit of  claim 2 , wherein the conductive element includes a conductive trace extending within at least one of the one or more dielectric layers and electrically connected to a conductive bond pad exposed at the second dielectric surface and configured to be bonded to the external component. 
     
     
       10. A microelectronic assembly, comprising:
 a microelectronic unit, including:
 an epitaxial silicon layer having a front silicon surface and a back silicon surface opposite the front silicon surface, the epitaxial silicon layer having a source and a drain each extending between the front and back silicon surfaces, the source and the drain being doped portions of the epitaxial silicon layer; 
 a buried oxide layer having a top oxide surface and a bottom oxide surface opposite the top oxide surface, the top oxide surface facing the back silicon surface of the silicon epitaxial silicon layer; 
 an ohmic contact extending through the buried oxide layer between the top and bottom oxide surfaces, the ohmic contact being coupled to a lower surface of one of the source or the drain; 
 one or more dielectric layers having a first dielectric surface and a second dielectric surface opposite the first dielectric surface, the first dielectric surface facing the bottom oxide surface of the buried oxide layer; and 
 a conductive element extending through the one or more dielectric layers between the first and second dielectric surfaces, the conductive element being coupled to a lower surface of the ohmic contact; and 
 
 an external component having electrically conductive features at an exposed surface thereof, at least one of the electrically conductive features being electrically connected with the conductive element of the microelectronic unit.