Inventor · disambiguated record
Javier A. Delacruz
Also filed as: DELACRUZ JAVIER · DELACRUZ JAVIER A · DELACRUZ JAVIER ANDRES
146 granted patents·37 pending applications·3,404 citations·filing 1998–2025
99Inventor score
Files withXCELSIS CORP37INVENSAS CORP33ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC30ADEIA SEMICONDUCTOR INC25INVENSAS BONDING TECH INC23
Top patents by PatentIndex Score
183 records- 0199US11817409B2Directly bonded structures without intervening adhesive and methods for forming the sameADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC·Filed 2021·Granted Nov 14, 2023·13 cites·30 claims
- 0299US11557516B23D chip with shared clock distribution networkADEIA SEMICONDUCTOR INC·Filed 2020·Granted Jan 17, 2023·7 cites·22 claims
- 0399US11476213B2Bonded structures without intervening adhesiveINVENSAS BONDING TECH INC·Filed 2020·Granted Oct 18, 2022·50 cites·22 claims
- 0499US11348898B2Systems and methods for releveled bump planes for chipletsXCELSIS CORP·Filed 2020·Granted May 31, 2022·144 cites·17 claims
- 0599US11264357B1Mixed exposure for large dieINVENSAS CORP·Filed 2020·Granted Mar 1, 2022·145 cites·22 claims
- 0699US10991804B2Transistor level interconnection methodologies utilizing 3D interconnectsXCELSIS CORP·Filed 2019·Granted Apr 27, 2021·144 cites·10 claims
- 0799US10950547B2Stacked IC structure with system level wiring on multiple sides of the IC dieXCELSIS CORP·Filed 2020·Granted Mar 16, 2021·145 cites·19 claims
- 0899US10886177B23D chip with shared clock distribution networkXCELSIS CORP·Filed 2020·Granted Jan 5, 2021·148 cites·20 claims
- 0999US10672663B23D chip sharing power circuitXCELSIS CORP·Filed 2018·Granted Jun 2, 2020·25 cites·24 claims
- 1099US10580757B2Face-to-face mounted IC dies with orthogonal top interconnect layersXCELSIS CORP·Filed 2018·Granted Mar 3, 2020·25 cites·20 claims
- 1198US12100684B2Bonded structuresADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC·Filed 2022·Granted Sep 24, 2024·3 cites·26 claims
- 1298US11916076B2Device disaggregation for improved performanceADEIA SEMICONDUCTOR INC·Filed 2020·Granted Feb 27, 2024·12 cites·32 claims
- 1398US11876076B2Apparatus for non-volatile random access memory stacksADEIA SEMICONDUCTOR TECH LLC·Filed 2020·Granted Jan 16, 2024·7 cites·31 claims
- 1498US11860415B2Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnectsADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC·Filed 2021·Granted Jan 2, 2024·9 cites·17 claims
- 1598US11848284B2Protective elements for bonded structuresADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC·Filed 2022·Granted Dec 19, 2023·7 cites·16 claims
- 1698US11728287B2Wafer-level bonding of obstructive elementsADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC·Filed 2021·Granted Aug 15, 2023·7 cites·36 claims
- 1798US11721653B2Circuitry for electrical redundancy in bonded structuresADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC·Filed 2020·Granted Aug 8, 2023·12 cites·21 claims
- 1898US11670615B2Bonded structuresADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC·Filed 2020·Granted Jun 6, 2023·6 cites·23 claims
- 1998US11610846B2Protective elements for bonded structures including an obstructive elementADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC·Filed 2020·Granted Mar 21, 2023·9 cites·18 claims
- 2098US11600542B2Cavity packagesADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC·Filed 2021·Granted Mar 7, 2023·6 cites·23 claims
- 2198US11515291B2Integrated voltage regulator and passive componentsADEIA SEMICONDUCTOR INC·Filed 2019·Granted Nov 29, 2022·38 cites·18 claims
- 2298US11385278B2Security circuitry for bonded structuresINVENSAS BONDING TECH INC·Filed 2020·Granted Jul 12, 2022·60 cites·27 claims
- 2398US11373963B2Protective elements for bonded structuresINVENSAS BONDING TECH INC·Filed 2020·Granted Jun 28, 2022·52 cites·27 claims
- 2498US11355443B2Dielets on flexible and stretchable packaging for microelectronicsINVENSAS CORP·Filed 2019·Granted Jun 7, 2022·144 cites·9 claims
- 2598US11296044B2Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processesINVENSAS BONDING TECH INC·Filed 2019·Granted Apr 5, 2022·80 cites·24 claims
- 2698US11205625B2Wafer-level bonding of obstructive elementsINVENSAS BONDING TECH INC·Filed 2020·Granted Dec 21, 2021·68 cites·28 claims
- 2798US11169326B2Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnectsINVENSAS BONDING TECH INC·Filed 2019·Granted Nov 9, 2021·60 cites·22 claims
- 2898US11127738B2Back biasing of FD-SOI circuit blocksXCELSIS CORP·Filed 2018·Granted Sep 21, 2021·144 cites·18 claims
- 2998US10923413B2Hard IP blocks with physically bidirectional passagewaysXCELSIS CORP·Filed 2019·Granted Feb 16, 2021·144 cites·18 claims
- 3098US10923408B2Cavity packagesINVENSAS BONDING TECH INC·Filed 2018·Granted Feb 16, 2021·133 cites·17 claims
- 3198US10784191B2Interface structures and methods for forming sameINVENSAS BONDING TECH INC·Filed 2018·Granted Sep 22, 2020·123 cites·24 claims
- 3298US10719762B2Three dimensional chip structure implementing machine trained networkXCELSIS CORP·Filed 2017·Granted Jul 21, 2020·20 cites·21 claims
- 3398US10672744B23D compute circuit with high density Z-axis interconnectsXCELSIS CORP·Filed 2018·Granted Jun 2, 2020·27 cites·20 claims
- 3498US10672745B23D processorXCELSIS CORP·Filed 2018·Granted Jun 2, 2020·25 cites·20 claims
- 3598US10672743B23D Compute circuit with high density z-axis interconnectsXCELSIS CORP·Filed 2018·Granted Jun 2, 2020·23 cites·23 claims
- 3698US10607136B2Time borrowing between layers of a three dimensional chip stackXCELSIS CORP·Filed 2017·Granted Mar 31, 2020·21 cites·22 claims
- 3798US10600691B23D chip sharing power interconnect layerXCELSIS CORP·Filed 2018·Granted Mar 24, 2020·24 cites·24 claims
- 3898US10600735B23D chip sharing data busXCELSIS CORP·Filed 2018·Granted Mar 24, 2020·21 cites·21 claims
- 3998US10586786B23D chip sharing clock interconnect layerXCELSIS CORP·Filed 2018·Granted Mar 10, 2020·22 cites·24 claims
- 4098US10580735B2Stacked IC structure with system level wiring on multiple sides of the IC dieXCELSIS CORP·Filed 2018·Granted Mar 3, 2020·21 cites·20 claims
- 4198US10522352B2Direct-bonded native interconnects and active base dieXCELSIS CORP·Filed 2017·Granted Dec 31, 2019·20 cites·23 claims
- 4298US10522499B2Bonded structuresINVENSAS BONDING TECH INC·Filed 2017·Granted Dec 31, 2019·137 cites·28 claims
- 4398US10446487B2Interface structures and methods for forming sameINVENSAS BONDING TECH INC·Filed 2017·Granted Oct 15, 2019·151 cites·28 claims
- 4498US10269708B2Increased contact alignment tolerance for direct bondingINVENSAS BONDING TECH INC·Filed 2017·Granted Apr 23, 2019·49 cites·20 claims
- 4598US10002844B1Bonded structuresINVENSAS BONDING TECH INC·Filed 2016·Granted Jun 19, 2018·167 cites·20 claims
- 4698US9852988B2Increased contact alignment tolerance for direct bondingINVENSAS BONDING TECH INC·Filed 2016·Granted Dec 26, 2017·218 cites·20 claims
- 4797US12308332B2Circuitry for electrical redundancy in bonded structuresADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC·Filed 2024·Granted May 20, 2025·2 cites·22 claims
- 4897US12142528B23D chip with shared clock distribution networkADEIA SEMICONDUCTOR INC·Filed 2022·Granted Nov 12, 2024·2 cites·26 claims
- 4997US11824046B2Symbiotic network on layersADEIA SEMICONDUCTOR TECH LLC·Filed 2022·Granted Nov 21, 2023·2 cites·16 claims
- 5097US11626363B2Bonded structures with integrated passive componentADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC·Filed 2017·Granted Apr 11, 2023·16 cites·25 claims
Showing the top 50 of 183 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →