Assignee
CHARTERED SEMICONDUCTOR MFG
SG·925 granted patents·73 pending applications·30,087 citations·filing 1991–2010
Top patents by PatentIndex Score
998 records- 0199US6284657B1Non-metallic barrier formation for copper damascene type interconnectsCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Sep 4, 2001·190 cites·20 claims
- 0299US5989978AShallow trench isolation of MOSFETS with reduced corner parasitic currentsCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Nov 23, 1999·393 cites·22 claims
- 0398US7592270B2Modulation of stress in stress film through ion implantation and its application in stress memorization techniqueCHARTERED SEMICONDUCTOR MFG·Filed 2007·Granted Sep 22, 2009·58 cites·32 claims
- 0498US6743291B2Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growthCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jun 1, 2004·125 cites·28 claims
- 0598US6492726B1Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnectionCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Dec 10, 2002·267 cites·28 claims
- 0698US6376353B1Aluminum and copper bimetallic bond pad scheme for copper damascene interconnectsCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Apr 23, 2002·319 cites·52 claims
- 0798US6348407B1Method to improve adhesion of organic dielectrics in dual damascene interconnectsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Feb 19, 2002·250 cites·34 claims
- 0898US6303418B1Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layerCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Oct 16, 2001·374 cites·28 claims
- 0997US7939348B2E-beam inspection structure for leakage analysisCHARTERED SEMICONDUCTOR MFG·Filed 2007·Granted May 10, 2011·85 cites·20 claims
- 1097US7902548B2Planar voltage contrast test structureCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Mar 8, 2011·84 cites·10 claims
- 1197US7867835B2Integrated circuit system for suppressing short channel effectsCHARTERED SEMICONDUCTOR MFG·Filed 2008·Granted Jan 11, 2011·116 cites·20 claims
- 1297US6538333B2Three dimensional IC package moduleCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Mar 25, 2003·369 cites·6 claims
- 1397US6475908B1Dual metal gate process: metals and their silicidesCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Nov 5, 2002·128 cites·42 claims
- 1497US6300177B1Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materialsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 9, 2001·175 cites·26 claims
- 1597US6287979B1Method for forming an air gap as low dielectric constant material using buckminsterfullerene as a porogen in an air bridge or a sacrificial layerCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Sep 11, 2001·140 cites·29 claims
- 1697US6136693AMethod for planarized interconnect vias using electroless plating and CMPCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Oct 24, 2000·289 cites·34 claims
- 1797US5870121ATi/titanium nitride and ti/tungsten nitride thin film resistors for thermal ink jet technologyCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Feb 9, 1999·140 cites·12 claims
- 1897US5710070AApplication of titanium nitride and tungsten nitride thin film resistor for thermal ink jet technologyCHARTERED SEMICONDUCTOR MFG·Filed 1996·Granted Jan 20, 1998·146 cites·20 claims
- 1996US7718500B2Formation of raised source/drain structures in NFET with embedded SiGe in PFETCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted May 18, 2010·53 cites·22 claims
- 2096US7479425B2Method for forming high-K charge storage deviceCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Jan 20, 2009·40 cites·28 claims
- 2196US7169675B2Material architecture for the fabrication of low temperature transistorCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Jan 30, 2007·164 cites·49 claims
- 2296US6461900B1Method to form a self-aligned CMOS inverter using vertical device integrationCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 8, 2002·141 cites·22 claims
- 2396US6444576B1Three dimensional IC package moduleCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Sep 3, 2002·163 cites·4 claims
- 2496US6410376B1Method to fabricate dual-metal CMOS transistors for sub-0.1 μm ULSI integrationCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 25, 2002·165 cites·34 claims
- 2596US6358842B1Method to form damascene interconnects with sidewall passivation to protect organic dielectricsCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Mar 19, 2002·141 cites·30 claims
- 2696US6352917B1Reversed damascene process for multiple level metal interconnectsCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Mar 5, 2002·140 cites·34 claims
- 2796US6348385B1Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constantCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Feb 19, 2002·128 cites·12 claims
- 2896US6265321B1Air bridge process for forming air gapsCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Jul 24, 2001·148 cites·37 claims
- 2996US6261935B1Method of forming contact to polysilicon gate for MOS devicesCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jul 17, 2001·216 cites·28 claims
- 3096US5858876ASimultaneous deposit and etch method for forming a void-free and gap-filling insulator layer upon a patterned substrate layerCHARTERED SEMICONDUCTOR MFG·Filed 1996·Granted Jan 12, 1999·338 cites·24 claims
- 3196US5731239AMethod of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistanceCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Mar 24, 1998·174 cites·19 claims
- 3295US7405131B2Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressorCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Jul 29, 2008·45 cites·26 claims
- 3395US7271110B2High density plasma and bias RF power process to make stable FSG with less free F and SiN with less H to enhance the FSG/SiN integration reliabilityCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Sep 18, 2007·32 cites·18 claims
- 3495US7109099B2End of range (EOR) secondary defect engineering using substitutional carbon dopingCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Sep 19, 2006·102 cites·20 claims
- 3595US6458695B1Methods to form dual metal gates by incorporating metals and their conductive oxidesCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 1, 2002·83 cites·30 claims
- 3695US6297132B1Process to control the lateral doping profile of an implanted channel regionCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Oct 2, 2001·128 cites·18 claims
- 3795US6197705B1Method of silicon oxide and silicon glass films depositionCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Mar 6, 2001·299 cites·5 claims
- 3895US6040243AMethod to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusionCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Mar 21, 2000·250 cites·20 claims
- 3995US5856225ACreation of a self-aligned, ion implanted channel region, after source and drain formationCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Jan 5, 1999·253 cites·22 claims
- 4095US5595919AMethod of making self-aligned halo process for reducing junction capacitanceCHARTERED SEMICONDUCTOR MFG·Filed 1996·Granted Jan 21, 1997·175 cites·28 claims
- 4195US5330930AFormation of vertical polysilicon resistor having a nitride sidewall for small static RAM cellCHARTERED SEMICONDUCTOR MFG·Filed 1992·Granted Jul 19, 1994·176 cites·18 claims
- 4294US6897118B1Method of multiple pulse laser annealing to activate ultra-shallow junctionsCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted May 24, 2005·105 cites·38 claims
- 4394US6884712B2Method of manufacturing semiconductor local interconnect and contactCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Apr 26, 2005·233 cites·10 claims
- 4494US6747314B2Method to form a self-aligned CMOS inverter using vertical device integrationCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jun 8, 2004·93 cites·11 claims
- 4594US6706625B1Copper recess formation using chemical process for fabricating barrier cap for lines and viasCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Mar 16, 2004·171 cites·64 claims
- 4694US6683002B1Method to create a copper diffusion deterrent interfaceCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Jan 27, 2004·71 cites·7 claims
- 4794US6436824B1Low dielectric constant materials for copper damasceneCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Aug 20, 2002·175 cites·28 claims
- 4894US6424044B1Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallizationCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jul 23, 2002·99 cites·13 claims
- 4994US6313008B1Method to form a balloon shaped STI using a micro machining technique to remove heavily doped siliconCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Nov 6, 2001·90 cites·30 claims
- 5094US5801083AUse of polymer spacers for the fabrication of shallow trench isolation regions with rounded top cornersCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Sep 1, 1998·251 cites·16 claims
Showing the top 50 of 998 patent records by PatentIndex Score.
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