Formation of raised source/drain structures in NFET with embedded SiGe in PFET

Abstract

A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains.

1. A method for forming a semiconductor device comprising the steps of:
 providing a N-doped field effect transistor (NFET) gate structure over a NFET region in a substrate and a P-doped field effect transistor (PFET) gate structure over a PFET region, wherein a gate structure comprises first and second spacers on sidewalls and a cap layer; 
 providing NFET source drain extension (SDE) regions adjacent to said NFET gate; and providing PFET SDE regions adjacent to said PFET gate; 
 forming recesses in said PFET region in the substrate adjacent to said PFET second spacers; 
 forming a PFET embedded Source/drain stressor in the recesses; 
 forming a NFET source drain (S/D) epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor, wherein the NFET S/D epitaxial layer comprises a faster growth rate than the PFET S/D epitaxial Si layer; 
 removing the cap layer on the PFET and NFET gate structures and reducing second spacers of the gate structures to form reduced second PFET spacers and reduced second NFET spacers; and 
 performing a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D epitaxial Si layer to form the raised NFET source/drains. 
 
   
   
     2. A method for forming a semiconductor device comprising the steps of:
 a) proving NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region;
 (1) said NFET gate structure is comprised of a NFET gate dielectric, a NFET gate, 
 
 NFET gate cap, NFET first spacers, NFET second spacers;
 (2) said PFET gate structure is comprised of a PFET gate dielectric, a PFET gate, 
 
 PFET gate cap, PFET first spacers, and PFET second spacers; 
 b) providing NFET SDE regions adjacent to said NFET gate; and providing PFET SDE regions adjacent to said PFET gate; 
 c) forming recesses in said PFET region in the substrate adjacent to said PFET second spacers; 
 d) forming a PFET embedded Source/drain stressor using an in-situ Boron doped SiGe epitaxy process; 
 e) forming a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor;
 (1) the NFET S/D epitaxial Si layer is thicker than the PFET S/D epitaxial Si layer; 
 
 f) etching and removing the PFET gate cap and the NFET gate cap and removing said second PFET spacers and said second NFET spacer 
 g) forming reduced second PFET spacers and reduced second NFET spacers; 
 h) performing a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D epitaxial Si layer to form the NFET raised Source/drains; 
 i) forming silicide regions over the NFET raised source/drain regions and the PFET embedded source/drain stressor. 
 
   
   
     3. The method of  claim 2  which further includes: forming a stressor layer over the substrate and NFET gate structure and PFET gate structure. 
   
   
     4. A method for forming a semiconductor device comprising:
 providing a substrate having first and second active regions, wherein the first and second active regions are prepared with first and second transistor gate structures of first and second transistors, wherein a gate structure comprises first and second spacers and a cap layer; 
 forming recesses in the second active region adjacent to the second transistor gate structure; 
 filling the recesses with a fill layer; 
 forming first source/drain (s/d) layers in the first active region adjacent to the first gate structure and second s/d layers over the recesses in the second active region, wherein the first s/d layers comprise a faster growth rate than the second s/d layers; and 
 removing caps over the first and second gate structures and reducing second sidewall spacers on the first and second gate structures. 
 
   
   
     5. The method of  claim 4  wherein the first transistor comprises a n-type transistor and the second transistor comprises a p-type transistor. 
   
   
     6. The method of  claim 4  wherein the fill layer comprises a SiGe layer and the s/d layers comprise a Si layer. 
   
   
     7. The method of  claim 4  comprises implanting first type ions into the first active region, wherein the first type ions comprise n-type ions. 
   
   
     8. The method of  claim 4  wherein the fill layer comprises a SiGe layer doped with second type ions. 
   
   
     9. The method of  claim 8  wherein the fill layer is formed using an in-situ epitaxy process. 
   
   
     10. The method of  claim 8  wherein the second type ions comprise p-type ions. 
   
   
     11. The method of  claim 4  further includes forming a stressor layer over the substrate and first and second transistor gate structures. 
   
   
     12. A method for forming a semiconductor device comprising:
 providing a substrate having first and second active regions, wherein the first and second active regions are prepared with first and second transistor gate structures of first and second transistors, wherein the first and second gate structures include caps over the gate structures and first and second sidewall spacers on sidewalls of the gate structures; 
 forming stressors in the second active region adjacent to the second transistor gate structure; and 
 forming first s/d layers on the substrate in the first active region adjacent the first gate structure and second s/d layers on the stressors in the second active region, wherein the first s/d layers comprise a faster growth rate than the second s/d layers; 
 removing caps over the first and second gate structures; and 
 reducing the second sidewall spacers on the first and second gate structures. 
 
   
   
     13. The method of  claim 12  wherein the first transistor comprises n-type transistor and the second transistor comprises a p-type transistor. 
   
   
     14. The method of  claim 13  wherein:
 the stressors comprise a top surface above the substrate; and 
 the first and second s/d layers form first and second raised s/d structures of the first and second transistors, the first and second raised s/d structures having top surfaces which are about coplanar. 
 
   
   
     15. The method of  claim 12  wherein the stressors comprise a top surface above the substrate. 
   
   
     16. The method of  claim 12  wherein first and second s/d layers form first and second raised s/d structures of the first and second transistors, the first and second raised s/d structures having top surfaces which are about coplanar. 
   
   
     17. The method of  claim 12  comprises implanting first type ions into the first s/d layer over the first active region to form raised diffusion structures. 
   
   
     18. The method of  claim 12  wherein the stressors comprises SiGe doped with ions of a second type. 
   
   
     19. The method of  claim 18  wherein the second type ions comprises p-type. 
   
   
     20. The method of  claim 12  wherein forming stressors comprises:
 recessing the substrate in the second active region adjacent to the second gate structure; and 
 filling the recess with stress inducing material. 
 
   
   
     21. The method of  claim 12  wherein the stressors comprises SiGe doped with ions of a second type and the first and second s/d layers comprise Si. 
   
   
     22. The method of  claim 12  wherein forming stressors comprises:
 recessing the substrate in the second active region adjacent to the second gate structure using a selective isotropic etch to form recesses with undercut under the second gate structure; and 
 filling the recess with stress inducing material.