Assignee
COTEUS PAUL W
US·12 granted patents·1 pending application·77 citations·filing 2006–2012
Top patents by PatentIndex Score
13 records- 0197US8516409B2Implementing vertical die stacking to distribute logical function over multiple dies in through-silicon-via stacked semiconductor deviceCOTEUS PAUL W·Filed 2010·Granted Aug 20, 2013·41 cites·4 claims
- 0284US8289798B2Voltage regulator bypass in memory deviceCOTEUS PAUL W·Filed 2010·Granted Oct 16, 2012·9 cites·18 claims
- 0381US9053811B2Memory device refreshCOTEUS PAUL W·Filed 2012·Granted Jun 9, 2015·7 cites·19 claims
- 0480US8495328B2Providing frame start indication in a memory system having indeterminate read data latencyCOTEUS PAUL W·Filed 2012·Granted Jul 23, 2013·3 cites·10 claims
- 0577US8174106B2Through board stacking of multiple LGA-connected componentsCOTEUS PAUL W·Filed 2006·Granted May 8, 2012·6 cites·20 claims
- 0672US8145868B2Method and system for providing frame start indication in a memory system having indeterminate read data latencyCOTEUS PAUL W·Filed 2007·Granted Mar 27, 2012·3 cites·8 claims
- 0768US8151042B2Method and system for providing identification tags in a memory system having indeterminate data response timesCOTEUS PAUL W·Filed 2007·Granted Apr 3, 2012·2 cites·20 claims
- 0866US8278745B2Through board stacking of multiple LGA-connected componentsCOTEUS PAUL W·Filed 2009·Granted Oct 2, 2012·2 cites·13 claims
- 0961US9037892B2System-wide power management control via clock distribution networkCOTEUS PAUL W·Filed 2011·Granted May 19, 2015·1 cites·27 claims
- 1058US8185800B2System for error control coding for memories of different types and associated methodsCOTEUS PAUL W·Filed 2008·Granted May 22, 2012·3 cites·21 claims
- 1155US8327105B2Providing frame start indication in a memory system having indeterminate read data latencyCOTEUS PAUL W·Filed 2012·Granted Dec 4, 2012·0 cites·9 claims
- 1246US2012043664A1Implementing multiple different types of dies for memory stackingCOTEUS PAUL W·Filed 2010·Application pending·0 cites
- 1339US8909878B2Implementing timing alignment and synchronized memory activities of multiple memory devices accessed in parallelCOTEUS PAUL W·Filed 2012·Granted Dec 9, 2014·0 cites·20 claims
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