Implementing multiple different types of dies for memory stacking

Abstract

A method and structure are provided for implementing multiple different types of dies for memory stacking. A common wafer is provided with a predefined reticle type. The reticle type includes a plurality of arrays, and a plurality of periphery segments. A plurality of through-silicon-vias (TSVs) is placed at boundaries between array and periphery segments. Multiple different types of dies for memory stacking are obtained based upon selected scribing of the dies from the common wafer.

What is claimed is: 
     
         1 . A method for implementing multiple different types of dies for memory stacking comprising:
 providing a reticle type includes a plurality of arrays, and a plurality of periphery segments;   placing a plurality of through-silicon-vias (TSVs) at boundaries between array and periphery segments;   providing a common wafer with said predefined reticle type; and   obtaining multiple different types of the dies based upon selected scribing of dies from the common wafer.   
     
     
         2 . The method as recited in  claim 1  wherein providing a reticle type includes a plurality of arrays, and a plurality of periphery segments includes providing first and second pairs of arrays on opposed sides of the periphery segment. 
     
     
         3 . The method as recited in  claim 2  further includes placing said plurality of through-silicon-vias (TSVs) at opposed boundaries between said first and second pairs of arrays and the periphery segment. 
     
     
         4 . The method as recited in  claim 1  wherein providing a reticle type includes a plurality of arrays, and a plurality of periphery segments includes providing adjacent pairs of arrays spaced apart by a pair of arrays from the periphery segment. 
     
     
         5 . The method as recited in  claim 4  further includes placing a plurality of through-silicon-vias (TSVs) at a boundary between said adjacent pairs of arrays. 
     
     
         6 . The method as recited in  claim 1  wherein obtaining multiple different types of the dies based upon selected scribing of dies from the common wafer includes scribing of dies including first and second pair of said arrays and one said periphery segment and said plurality of through-silicon-vias (TSVs) at boundaries between said first and second pair of said arrays and one said periphery segment. 
     
     
         7 . The method as recited in  claim 1  wherein obtaining multiple different types of the dies based upon selected scribing of dies from the common wafer includes scribing of dies including a plurality of through-silicon-vias (TSVs) and arrays only. 
     
     
         8 . The method as recited in  claim 1  wherein obtaining multiple different types of the dies based upon selected scribing of dies from the common wafer includes scribing of dies including a plurality of through-silicon-vias (TSVs) and one said periphery segment only. 
     
     
         9 . The method as recited in  claim 1  includes forming a memory stack with a first die mounted on a printed circuit board (PCB). 
     
     
         10 . The method as recited in  claim 9  includes obtaining said first die including a plurality of through-silicon-vias (TSVs) and first and second pairs of arrays and one said periphery segment. 
     
     
         11 . The method as recited in  claim 9  includes obtaining said first die including plurality of through-silicon-vias (TSVs) and one said periphery segment. 
     
     
         12 . The method as recited in  claim 10  further includes obtaining a plurality of second dies including through-silicon-vias (TSVs) and arrays only; mounting said second dies and said first die in the memory stack connected by said TSVs. 
     
     
         13 . The method as recited in  claim 11  further includes obtaining a plurality of second dies including through-silicon-vias (TSVs) and arrays only; mounting said second dies and said first die in the memory stack connected by said TSVs. 
     
     
         14 . A structure for implementing multiple different types of dies for memory stacking comprising:
 a reticle type includes a plurality of arrays, and a plurality of periphery segments;   a plurality of through-silicon-vias (TSVs) being disposed at boundaries between array and periphery segments;   a common wafer being defined with said predefined reticle type; and said multiple different types of the dies being obtained based upon selected scribing of the common wafer.   
     
     
         15 . The structure as recited in  claim 14  wherein said reticle type includes first and second pairs of arrays on opposed sides of the periphery segment, and said plurality of through-silicon-vias (TSVs) being disposed at opposed boundaries between said first and second pairs of arrays and the periphery segment. 
     
     
         16 . The structure as recited in  claim 14  wherein said reticle type includes adjacent pairs of arrays spaced apart by a pair of arrays from the periphery segment, and includes a plurality of through-silicon-vias (TSVs) being disposed at a boundary between said adjacent pairs of arrays. 
     
     
         17 . The structure as recited in  claim 14  wherein said multiple different types of the dies being obtained based upon selected scribing of the common wafer include first and second pair of said arrays and one said periphery segment and said plurality of through-silicon-vias (TSVs) being disposed at opposed boundaries between said first and second pairs of arrays and the periphery segment. 
     
     
         18 . The structure as recited in  claim 14  wherein said multiple different types of the dies being obtained based upon selected scribing of the common wafer include a plurality of through-silicon-vias (TSVs) and one said periphery segment only. 
     
     
         19 . The structure as recited in  claim 14  wherein said multiple different types of the dies being obtained based upon selected scribing of the common wafer include a plurality of through-silicon-vias (TSVs) and arrays only. 
     
     
         20 . The structure as recited in  claim 14  includes a memory stack with a first die mounted on a printed circuit board (PCB), and a plurality of second dies including through-silicon-vias (TSVs) and arrays only; and said second dies mounted on said first die in the memory stack connected by said TSVs.