Assignee
PECHANEK GERALD GEORGE
US·25 granted patents·1 pending application·103 citations·filing 2003–2020
Top patents by PatentIndex Score
26 records- 0195US7581079B2Processor composed of memory nodes that execute memory access instructions and cooperate with execution nodes to execute function instructionsPECHANEK GERALD GEORGE·Filed 2006·Granted Aug 25, 2009·36 cites·29 claims
- 0293US8443169B2Interconnection network connecting operation-configurable nodes according to one or more levels of adjacency in multiple dimensions of communication in a multi-processor and a neural processorPECHANEK GERALD GEORGE·Filed 2011·Granted May 14, 2013·18 cites·24 claims
- 0388US9460048B2Methods and apparatus for creating and executing a packet of instructions organized according to data dependencies between adjacent instructions and utilizing networks based on adjacencies to transport data in response to execution of the instructionsPECHANEK GERALD GEORGE·Filed 2013·Granted Oct 4, 2016·9 cites·26 claims
- 0486US8156311B2Interconnection networks and methods of construction thereof for efficiently sharing memory and processing in a multiprocessor wherein connections are made according to adjacency of nodes in a dimensionPECHANEK GERALD GEORGE·Filed 2010·Granted Apr 10, 2012·7 cites·20 claims
- 0583US8341381B2Twisted and wrapped array organized into clusters of processing elementsPECHANEK GERALD GEORGE·Filed 2007·Granted Dec 25, 2012·7 cites·20 claims
- 0681US9507603B2Methods and apparatus for signal flow graph pipelining that reduce storage of temporary variablesPECHANEK GERALD GEORGE·Filed 2014·Granted Nov 29, 2016·4 cites·13 claims
- 0776US9063722B2Methods and apparatus for independent processor node operations in a SIMD array processorPECHANEK GERALD GEORGE·Filed 2011·Granted Jun 23, 2015·3 cites·20 claims
- 0875US9390057B2Communicaton across shared mutually exclusive direction paths between clustered processing elementsPECHANEK GERALD GEORGE·Filed 2012·Granted Jul 12, 2016·2 cites·20 claims
- 0972US8484444B2Methods and apparatus for attaching application specific functions within an array processorPECHANEK GERALD GEORGE·Filed 2011·Granted Jul 9, 2013·2 cites·20 claims
- 1070US8335812B2Methods and apparatus for efficient complex long multiplication and covariance matrix implementationPECHANEK GERALD GEORGE·Filed 2010·Granted Dec 18, 2012·2 cites·20 claims
- 1170US8296479B2System core for transferring data between an external device and memoryPECHANEK GERALD GEORGE·Filed 2012·Granted Oct 23, 2012·1 cites·20 claims
- 1270US8117357B2System core for transferring data between an external device and memoryPECHANEK GERALD GEORGE·Filed 2011·Granted Feb 14, 2012·1 cites·20 claims
- 1366US7886128B2Interconnection network and method of construction thereof for efficiently sharing memory and processing in a multi-processor wherein connections are made according to adjacency of nodes in a dimensionPECHANEK GERALD GEORGE·Filed 2009·Granted Feb 8, 2011·2 cites·23 claims
- 1465US7185177B2Methods and apparatus for meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processorsPECHANEK GERALD GEORGE·Filed 2003·Granted Feb 27, 2007·8 cites·28 claims
- 1561US10503515B2Methods and apparatus for adjacency network delivery of operands to instruction specified destinations that reduces storage of temporary variablesPECHANEK GERALD GEORGE·Filed 2018·Granted Dec 10, 2019·0 cites·20 claims
- 1661US8266410B2Meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processorsPECHANEK GERALD GEORGE·Filed 2009·Granted Sep 11, 2012·1 cites·24 claims
- 1757US10078517B2Methods and apparatus for signal flow graph pipelining in an array processing unit that reduces storage of temporary variablesPECHANEK GERALD GEORGE·Filed 2016·Granted Sep 18, 2018·0 cites·22 claims
- 1857US8397000B2System core for transferring data between an external device and memoryPECHANEK GERALD GEORGE·Filed 2012·Granted Mar 12, 2013·0 cites·20 claims
- 1956US7962723B2Methods and apparatus storing expanded width instructions in a VLIW memory deferred executionPECHANEK GERALD GEORGE·Filed 2009·Granted Jun 14, 2011·0 cites·20 claims
- 2055US2013283007A1Methods and Apparatus For Attaching Application Specific Functions Within An Array ProcessorPECHANEK GERALD GEORGE·Filed 2013·Application pending·0 cites
- 2154US9672033B2Methods and apparatus for transforming, loading, and executing super-set instructionsPECHANEK GERALD GEORGE·Filed 2009·Granted Jun 6, 2017·0 cites·21 claims
- 2253US9075651B2Methods and apparatus for efficient complex long multiplication and covariance matrix implementationPECHANEK GERALD GEORGE·Filed 2012·Granted Jul 7, 2015·0 cites·20 claims
- 2353US8671266B2Staging register file for use with multi-stage execution unitsPECHANEK GERALD GEORGE·Filed 2011·Granted Mar 11, 2014·0 cites·20 claims
- 2452US8069337B2Methods and apparatus for dynamic instruction controlled reconfigurable register filePECHANEK GERALD GEORGE·Filed 2011·Granted Nov 29, 2011·0 cites·20 claims
- 2551US8103854B1Methods and apparatus for independent processor node operations in a SIMD array processorPECHANEK GERALD GEORGE·Filed 2010·Granted Jan 24, 2012·0 cites·9 claims
- 2644US11249939B2Methods and apparatus for sharing nodes in a network with connections based on 1 to k+1 adjacency used in an execution array memory array (XarMa) processorPECHANEK GERALD GEORGE·Filed 2020·Granted Feb 15, 2022·0 cites·20 claims
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