Methods and Apparatus For Attaching Application Specific Functions Within An Array Processor

Abstract

A multi-node video signal processor (VSP N ) is describes that tightly couples multiple multi-cycle state machines (hardware assist units) to each processor and each memory in each node of an N node scalable array processor. VSP N memory hardware assist instructions are used to initiate multi-cycle state machine functions, to pass parameters to the multi-cycle state machines, to fetch operands from a node's memory, and to control the transfer of results from the multi-cycle state machines.

We claim: 
     
         1 . An apparatus for providing additional processing capability to a processor, the apparatus comprising:
 a first data memory having a first plurality of memory blocks and a second data memory having a second plurality of memory blocks;   a processing element (PE) selectively coupled to the first data memory and configured to access a first plurality of data values that are a power of two data type from the first plurality of memory blocks; and   a first hardware assist (HA) unit separately coupled to the PE, selectively coupled to the second data memory, and configured by the PE to access a second plurality of data values that are not a power of two data type from the second plurality of memory blocks in parallel with operations on the PE.   
     
     
         2 . The apparatus of  claim 1 , wherein the PE is selectively coupled to the second data memory, the first HA unit is selectively coupled to the first data memory, and the first HA unit is configured by the PE to access a third plurality of data values that are not a power of two data type from the first plurality of memory blocks in parallel with the PE accessing a fourth plurality of data values that are a power of two data type from the second plurality of memory blocks. 
     
     
         3 . The apparatus of  claim 1 , wherein the memory blocks are K×W-bit memory blocks with K and W power of two values. 
     
     
         4 . The apparatus of  claim 1 , wherein the second plurality of data values that are not a power of two data type are a plurality of 10-bit pixel values. 
     
     
         5 . The apparatus of  claim 1 , wherein the second plurality of data values that are not a power of two data type are a plurality of 12-bit pixel values. 
     
     
         6 . The apparatus of  claim 1 , wherein the first plurality of data values that are a power of two data type are a plurality of 8-bit pixel values. 
     
     
         7 . The apparatus of  claim 1 , wherein the first HA unit further comprises:
 a multi-cycle state machine initiated by the PE to execute a high compute function.   
     
     
         8 . The apparatus of  claim 7 , wherein the high compute function is a motion estimation and compensation function. 
     
     
         9 . The apparatus of  claim 7 , wherein the high compute function is a deblocking filter. 
     
     
         10 . The apparatus of  claim 1  further comprises:
 a third data memory having a third plurality of memory blocks; and 
 a second hardware assist (HA) unit separately coupled to the PE, selectively coupled to the third data memory, and configured by the PE to access a third plurality of data values that are not a power of two data type from the third plurality of memory blocks in parallel with operations on the PE. 
 
     
     
         11 . The apparatus of  claim 10 , wherein the second HA unit operates in parallel with the first HA unit. 
     
     
         12 . The apparatus of  claim 1 , wherein the PE further comprises:
 an execution unit that is configured by an instruction that specifies an operation on the data values that are not a power of two data type.   
     
     
         13 . The apparatus of  claim 1 , wherein the first HA unit is configured by the PE through a transfer of parameters from the PE to the first HA unit over a command and data interface. 
     
     
         14 . A method for providing additional processing capability to a processor, the method comprising:
 receiving control information in a hardware assist (HA) unit from a processing element (PE) to configure a state machine in the HA unit for a high compute function; and   operating the state machine to fetch a first plurality of data values that are not a power of two data type from a first plurality of memory blocks in a first data memory in parallel with the PE accessing a second plurality of data values that are a power of two data type from a second plurality of memory blocks in a second data memory.   
     
     
         15 . The method of  claim 14  further comprising:
 operating on the first plurality of data values that are not a power of two in the HA unit to provide a high compute function and generate results that are not a power of two data type; and 
 operating on at least one result of the generated results in the PE by an execution unit that is configured by an instruction that specifies an operation on data that is not a power of two data type. 
 
     
     
         16 . The method of  claim 15 , wherein the high compute function is a video algorithm. 
     
     
         17 . The method of  claim 14 , further comprising:
 operating a direct memory access (DMA) controller to selectively transfer the first plurality of data values that are not a power of two data type from an external memory to the first plurality of memory blocks in the first data memory.   
     
     
         18 . An apparatus for providing additional processing capability to a processor, the apparatus comprising:
 a first processing element (PE) directly coupled to a first hardware assist (HA) unit, the first PE selectively coupled to a first data memory, the first HA unit selectively coupled to a second data memory, wherein the first PE accesses a first plurality of data values that are a power of two data type from the first data memory in parallel with the first HA unit accesses of a second plurality of data values that are not a power of two data type from the second data memory;   a second PE directly coupled to a second HA unit, the second PE selectively coupled to a third data memory, the second HA unit selectively coupled to a fourth data memory, wherein the second PE accesses a third plurality of data values that are a power of two data type from the third data memory in parallel with the second HA unit accesses of a fourth plurality of data values that are not a power of two data type from the fourth data memory; and   an array controlling function configured to dispatch instructions to the first PE and to the second PE that control operations on the first HA unit and the second HA unit.   
     
     
         19 . The apparatus of  claim 18 , wherein the first HA unit receives first control information from the first PE to configure a first state machine in the first HA unit for a first high compute function and wherein the second HA unit receives second control information from the second PE to configure a second state machine in the second HA unit for a second high compute function. 
     
     
         20 . The apparatus of  claim 18 , wherein the second plurality of data values that are not a power of two data type are a plurality of 10-bit pixel values and the fourth plurality of data values that are not a power of two data type are a different plurality of 10-bit pixel values.