Assignee
SCHEIPER THILO
DE·19 granted patents·12 pending applications·98 citations·filing 2010–2012
Top patents by PatentIndex Score
31 records- 0196US8722498B2Self-aligned fin transistor formed on a bulk substrate by late fin etchSCHEIPER THILO·Filed 2011·Granted May 13, 2014·28 cites·20 claims
- 0293US8241977B2Short channel transistor with reduced length variation by using amorphous electrode material during implantationSCHEIPER THILO·Filed 2010·Granted Aug 14, 2012·12 cites·19 claims
- 0391US8409942B2Replacement gate approach based on a reverse offset spacer applied prior to work function metal depositionSCHEIPER THILO·Filed 2010·Granted Apr 2, 2013·13 cites·20 claims
- 0490US8722500B2Methods for fabricating integrated circuits having gate to active and gate to gate interconnectsSCHEIPER THILO·Filed 2011·Granted May 13, 2014·10 cites·9 claims
- 0584US8404550B2Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinementSCHEIPER THILO·Filed 2010·Granted Mar 26, 2013·7 cites·16 claims
- 0681US9184095B2Contact bars with reduced fringing capacitance in a semiconductor deviceSCHEIPER THILO·Filed 2010·Granted Nov 10, 2015·6 cites·20 claims
- 0780US9048336B2Reduced threshold voltage-width dependency in transistors comprising high-k metal gate electrode structuresSCHEIPER THILO·Filed 2011·Granted Jun 2, 2015·4 cites·9 claims
- 0879US8916433B2Superior integrity of high-k metal gate stacks by capping STI regionsSCHEIPER THILO·Filed 2012·Granted Dec 23, 2014·5 cites·22 claims
- 0971US8664072B2Source and drain architecture in an active region of a P-channel transistor by tilted implantationSCHEIPER THILO·Filed 2012·Granted Mar 4, 2014·2 cites·19 claims
- 1070US8318564B2Performance enhancement in transistors comprising high-k metal gate stack by an early extension implantationSCHEIPER THILO·Filed 2010·Granted Nov 27, 2012·2 cites·17 claims
- 1168US8790973B2Workfunction metal stacks for a final metal gateSCHEIPER THILO·Filed 2012·Granted Jul 29, 2014·2 cites·15 claims
- 1268US8558290B2Semiconductor device with dual metal silicide regions and methods of making sameSCHEIPER THILO·Filed 2011·Granted Oct 15, 2013·2 cites·20 claims
- 1366US8709902B2Sacrificial spacer approach for differential source/drain implantation spacers in transistors comprising a high-k metal gate electrode structureSCHEIPER THILO·Filed 2011·Granted Apr 29, 2014·2 cites·24 claims
- 1466US8481374B2Semiconductor element comprising a low variation substrate diodeSCHEIPER THILO·Filed 2010·Granted Jul 9, 2013·2 cites·17 claims
- 1561US8609533B2Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contactsSCHEIPER THILO·Filed 2012·Granted Dec 17, 2013·1 cites·20 claims
- 1650US8536033B2SOI semiconductor device comprising a substrate diode and a film diode formed by using a common well implantation maskSCHEIPER THILO·Filed 2011·Granted Sep 17, 2013·0 cites·16 claims
- 1750US2012280277A1Short channel transistor with reduced length variation by using amorphous electrode material during implantationSCHEIPER THILO·Filed 2012·Application pending·0 cites
- 1843US8609509B2Superior integrity of high-k metal gate stacks by forming STI regions after gate metalsSCHEIPER THILO·Filed 2011·Granted Dec 17, 2013·0 cites·23 claims
- 1942US8507348B2Field effect transistors for a flash memory comprising a self-aligned charge storage regionSCHEIPER THILO·Filed 2010·Granted Aug 13, 2013·0 cites·6 claims
- 2041US8815736B2Methods of forming metal silicide regions on semiconductor devices using different temperaturesSCHEIPER THILO·Filed 2011·Granted Aug 26, 2014·0 cites·14 claims
- 2141US2013295767A1Increased transistor performance by implementing an additional cleaning process in a stress liner approachSCHEIPER THILO·Filed 2012·Application pending·0 cites
- 2240US2013244388A1Methods for fabricating integrated circuits with reduced electrical parameter variationSCHEIPER THILO·Filed 2012·Application pending·0 cites
- 2339US2012196425A1High-K Metal Gate Electrode Structures Formed by a Replacement Gate Approach Based on Superior Planarity of Placeholder MaterialsSCHEIPER THILO·Filed 2012·Application pending·0 cites
- 2439US2013230948A1Multiple step implant process for forming source/drain regions on semiconductor devicesSCHEIPER THILO·Filed 2012·Application pending·0 cites
- 2538US2012156839A1Patterning of a Stressed Dielectric Material in a Contact Level Without Using an Underlying Etch Stop LayerSCHEIPER THILO·Filed 2011·Application pending·0 cites
- 2638US2011101427A1Transistor including a high-k metal gate electrode structure formed prior to drain/source regions on the basis of a superior implantation masking effectSCHEIPER THILO·Filed 2010·Application pending·0 cites
- 2738US2012049194A1Increased Charge Carrier Mobility in Transistors by Providing a Strain-Inducing Threshold Adjusting Semiconductor Material in the ChannelSCHEIPER THILO·Filed 2011·Application pending·0 cites
- 2838US2012025312A1Strain Engineering in Three-Dimensional Transistors Based on a Strained Channel Semiconductor MaterialSCHEIPER THILO·Filed 2011·Application pending·0 cites
- 2937US2011186937A1Adjustment of transistor characteristics based on a late well implantationSCHEIPER THILO·Filed 2010·Application pending·0 cites
- 3036US2011127614A1Reducing the series resistance in sophisticated transistors by embedding metal silicide contact regions reliably into highly doped semiconductor materialSCHEIPER THILO·Filed 2010·Application pending·0 cites
- 3136US2012049291A1Polysilicon Resistors Formed in a Semiconductor Device Comprising High-K Metal Gate Electrode StructuresSCHEIPER THILO·Filed 2011·Application pending·0 cites
Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →