Short channel transistor with reduced length variation by using amorphous electrode material during implantation

Abstract

In sophisticated transistor elements, enhanced profile uniformity along the transistor width direction may be accomplished by using a gate material in an amorphous state, thereby reducing channeling effects and line edge roughness. In sophisticated high-k metal gate approaches, an appropriate sequence may be applied to avoid a change of the amorphous state prior to performing the critical implantation processes for forming drain and source extension regions and halo regions.

1 .- 20 . (canceled) 
     
     
         21 . A transistor device, comprising:
 a gate electrode structure comprising:
 a high-k gate insulation material formed above a channel region of said transistor; 
 a metal-containing material formed on said high-k gate insulation material, and 
 at least one metal-containing electrode material formed on said metal-containing material; and 
   a sidewall spacer structure formed on sidewalls of said gate electrode structure, said sidewall spacer structure comprising an etch stop liner formed on a sidewall of said high-k dielectric material and a spacer element formed on said etch stop liner.   
     
     
         22 . The transistor device of  claim 21 , wherein a length of said gate electrode structure is approximately  40  nm or less. 
     
     
         23 . The transistor device of  claim 21 , further comprising a strain-inducing semiconductor alloy formed in drain and source areas of said transistor. 
     
     
         24 . The transistor device of  claim 21 , wherein said channel region comprises a threshold adjusting semiconductor alloy formed on a semiconductor layer. 
     
     
         25 . The transistor device of  claim 21 , wherein said metal-containing material formed on said high-k dielectric material comprises at least one of titanium and aluminum. 
     
     
         26 . The transistor device of  claim 21 , wherein said etch stop liner is formed over an entire length of said sidewalls of said gate electrode structure 
     
     
         27 . A transistor device, comprising:
 a gate electrode structure comprising:
 a high-k gate insulation material formed above a channel region of said transistor; 
 a metal-containing material formed on said high-k gate insulation material, and 
 at least one electrode material formed on said metal-containing material, wherein said at least one electrode material is at least partially formed from a material in an amorphous state; and 
   a sidewall spacer structure formed on sidewalls of said gate electrode structure, said sidewall spacer structure comprising an etch stop liner formed on a sidewall of said high-k dielectric material and a spacer element formed on said etch stop liner.   
     
     
         28 . The transistor device of  claim 27 , wherein a length of said gate electrode structure is approximately 40 nm or less. 
     
     
         29 . The transistor device of  claim 27 , further comprising a strain-inducing semiconductor alloy formed in drain and source areas of said transistor. 
     
     
         30 . The transistor device of  claim 27 , wherein said channel region comprises a threshold adjusting semiconductor alloy formed on a semiconductor layer. 
     
     
         31 . The transistor device of  claim 27 , wherein said metal-containing material formed on said high-k dielectric material comprises at least one of titanium and aluminum. 
     
     
         32 . The transistor device of  claim 27 , wherein said material in an amorphous state comprises a crystalline structure adapted to reduce one or more channeling effects. 
     
     
         33 . The transistor device of  claim 27 , wherein said at least one gate electrode material is formed from two or more segments of said material in an amorphous state. 
     
     
         34 . The transistor device of  claim 33 , wherein at least one of said two or more segments has an extension of approximately 100 nm and less. 
     
     
         35 . The transistor device of  claim 27 , wherein forming said at least one electrode material from said material in an amorphous state was performed using a high temperature treatment. 
     
     
         36 . A transistor device, comprising:
 a gate electrode structure comprising:
 a high-k gate insulation material formed above a channel region of said transistor; 
 a metal-containing material formed on said high-k gate insulation material, and 
 at least one metal-containing electrode material formed on said metal-containing material, wherein said at least one metal-containing electrode material is formed after removing a material in an amorphous state from said gate electrode structure; and 
   a sidewall spacer structure formed on sidewalls of said gate electrode structure, said sidewall spacer structure comprising an etch stop liner formed on a sidewall of said high-k dielectric material and a spacer element formed on said etch stop liner.   
     
     
         37 . The transistor device of  claim 27 , wherein a length of said gate electrode structure is approximately 40 nm or less. 
     
     
         38 . The transistor device of  claim 27 , further comprising a strain-inducing semiconductor alloy formed in drain and source areas of said transistor. 
     
     
         39 . The transistor device of  claim 27 , wherein said channel region comprises a threshold adjusting semiconductor alloy formed on a semiconductor layer. 
     
     
         40 . The transistor device of  claim 27 , wherein said metal-containing material formed on said high-k dielectric material comprises at least one of titanium and aluminum.